IP Library › Granted Patent US 12,262,589
Granted Patent B2
US 12,262,589 · App. 17/079,765 · Granted Mar 25, 2025

Pixel and display device comprising the same

Inventors: Keunwoo Kim (Yongin-si, KR); Hyena Kwak (Yongin-si, KR); Sangsub Kim (Yongin-si, KR); Hanbit Kim (Yongin-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
H10K59/1213G09G3/3233G09G3/3266G09G3/3275H10K59/1216H10K59/131
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Quick Facts
Patent No.
US 12,262,589
App. No.
17/079,765
Granted
Mar 25, 2025
Kind
B2
Abstract

A pixel includes: a driving transistor including a semiconductor layer and a gate electrode; and a compensation transistor connected to the gate electrode and the semiconductor layer of the driving transistor, wherein the first thin-film transistor includes: a first sub-transistor including a first gate electrode receiving a first scan signal having a first voltage level during a period; and a second sub-transistor connected to the first sub-transistor in parallel and comprising a second gate electrode receiving a second scan signal having a second voltage level that is an inverted level of the first voltage level during the same period.

Claims (57)

1. A pixel comprising:

a driving transistor comprising a gate electrode, a first terminal, and a second terminal;

a first transistor connected between a data line and the first terminal of the driving transistor where a gate electrode of the first transistor is connected to a first scan line; and

a second transistor connected between the gate electrode and the second terminal of the driving transistor,

wherein the second transistor comprises:

a first sub-transistor comprising a first gate electrode receiving a first scan signal from the first scan line having a first voltage level during a first period, a first terminal, and a second terminal; and

a second sub-transistor connected to the first sub-transistor in parallel and comprising a second gate electrode receiving a second scan signal having a second voltage level that is an inversion of the first voltage level during the first period, a first terminal, and a second terminal,

wherein the second terminal of the first sub-transistor and the second terminal of the second sub-transistor are connected to a node connected to the second terminal of the driving transistor, and

wherein the node is located between the driving transistor and an emission control transistor that is connected to an organic-light emitting diode,

wherein the first transistor, the first sub-transistor and the second sub-transistor are turned-on simultaneously, and the organic-light emitting diode does not emit light in the first period, and

wherein the first transistor, the first sub-transistor and the second sub-transistor are turned-off simultaneously, and the organic-light emitting diode emits light in a second period following the first period.

2. The pixel of claim 1 , wherein the first sub-transistor is a P-channel thin-film transistor, and the second sub-transistor is an N-channel thin-film transistor.

3. The pixel of claim 1 , further comprising:

a first scan line transmitting the first scan signal to the first sub-transistor and connected to the first sub-transistor; and

a second scan line transmitting the second scan signal to the second sub-transistor and connected to the second sub-transistor, wherein the first and second scan lines extend in parallel with the driving transistor therebetween.

4. The pixel of claim 1 , further comprising:

a first node electrode connecting the first terminal of the first sub-transistor and the gate electrode of the driving transistor to each other; and

a second node electrode connecting the first terminal of the second sub-transistor and the gate electrode of the driving transistor to each other.

5. The pixel of claim 4 , further comprising a capacitor overlapping the driving transistor.

6. The pixel of claim 4 , further comprising a driving voltage line, wherein the data line and the driving voltage line are disposed on a same layer as the first node electrode.

7. The pixel of claim 4 , wherein the driving transistor is a P-channel thin-film transistor.

8. The pixel of claim 1 , wherein each of the first sub-transistor and the second sub-transistor comprises a semiconductor layer comprising silicon.

9. The pixel of claim 1 , wherein the first sub-transistor comprises a semiconductor layer comprising silicon, and the second sub-transistor comprises a semiconductor layer comprising an oxide.

10. The pixel of claim 9 , further comprising a third transistor connected between the gate electrode of the driving transistor and an initialization voltage line.

11. The pixel of claim 10 , wherein the third transistor comprises a semiconductor layer comprising an oxide.

12. A pixel comprising:

a driving transistor comprising a gate electrode, a first terminal, and a second terminal;

a first transistor connected between a data line and the first terminal of the driving transistor where a gate electrode of the first transistor is connected to a first scan line; and

a second transistor connected between the gate electrode and the second terminal of the driving transistor,

wherein the second transistor comprises:

a first sub-transistor comprising a first gate electrode receiving a first scan signal from the first scan line having a first voltage level during a first period and a second gate electrode receiving a second scan signal having a second voltage level that is an inversion of the first voltage level during the first period; and

a second sub-transistor connected to the first sub-transistor in series, and the second sub-transistor comprising a third gate electrode receiving the first scan signal from the first scan line, a first electrode, and a second electrode connected to a node located between the driving transistor and an emission control transistor that is connected to an organic-light emitting diode,

wherein the first transistor, the first sub-transistor and the second sub-transistor are turned-on simultaneously, and the organic-light emitting diode does not emit light in the first period, and

wherein the first transistor, the first sub-transistor and the second sub-transistor are turned-off simultaneously, and the organic-light emitting diode emits light in a second period following the first period.

13. The pixel of claim 12 , further comprising:

a first scan line connected to the first gate electrode of the first sub-transistor and the third gate electrode of the second sub-transistor; and

a second scan line connected to the second gate electrode of the first sub-transistor.

14. The pixel of claim 13 , wherein the second gate electrode is disposed on a lower layer of the first gate electrode, and the third gate electrode is disposed on a same layer as the first gate electrode.

15. The pixel of claim 12 , further comprising a capacitor overlapping the driving transistor.

16. The pixel of claim 12 , further comprising:

a node electrode connecting a first terminal of the second transistor and the gate electrode of the driving transistor to each other; and

a driving voltage line,

wherein the data line and the driving voltage line are disposed on a same layer as the node electrode.

17. A display device comprising a plurality of pixels, wherein each of the plurality of pixels comprises:

a driving transistor comprising a gate electrode, a first terminal and a second terminal;

a first transistor connected between a data line and the first terminal of the driving transistor where a gate electrode of the first transistor is connected to a first scan line; and

a second transistor connected between the gate electrode and the second terminal of the driving transistor,

wherein the second transistor comprises:

a first sub-transistor comprising a first gate electrode receiving a first scan signal from the first scan line having a first voltage level during a first period, a first terminal, and a second terminal; and

a second sub-transistor comprising a second gate electrode receiving a second scan signal having a second voltage level that is an inversion of the first voltage level during the first period, a first terminal, and a second terminal,

wherein the second terminal of the first sub-transistor and the second terminal of the second sub-transistor are connected a node connected to the second terminal of the driving transistor,

and

wherein the node is located between the driving transistor and an emission control transistor that is connected to an organic-light emitting diode,

wherein the first transistor, the first sub-transistor and the second sub-transistor are turned-on simultaneously, and the organic-light emitting diode does not emit light in the first period, and

wherein the first transistor, the first sub-transistor and the second sub-transistor are turned-off simultaneously, and the organic-light emitting diode emits light in a second period following the first period.

18. The display device of claim 17 , wherein the first sub-transistor and the second sub-transistor are connected in parallel, the first sub-transistor is a P-channel thin-film transistor, and the second sub-transistor is an N-channel thin-film transistor.

19. The display device of claim 18 , wherein the first sub-transistor comprises a semiconductor layer comprising silicon, and the second sub-transistor comprises a semiconductor layer comprising an oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2020
From: KIM, KEUNWOO; KWAK, HYENA; KIM, SANGSUB; KIM, HANBIT
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 054163/0588 →
Priority Claims (1)
KR 10-2020-0049482 · Apr 23, 2020 · national
Continuity (1)
Related Publication 20210335953A1 · Oct 28, 2021
References Cited (29)
US 8441421B2 · Han · 2013 [cited by examiner]
US 9746723B2 · Yang et al. · 2017 [cited by applicant]
US 10482817B2 · Kim et al. · 2019 [cited by applicant]
US 20050200618A1 · Kim · 2005 [cited by examiner]
US 20120019503A1 · Lee · 2012 [cited by applicant]
US 20130321376A1 · Kim · 2013 [cited by examiner]
US 20140198136A1 · Lee · 2014 [cited by examiner]
US 20140346968A1 · Meng · 2014 [cited by examiner]
US 20150249158A1 · Cheng · 2015 [cited by examiner]
US 20190088731A1 · Lee · 2019 [cited by examiner]
US 20190304373A1 · Wang et al. · 2019 [cited by applicant]
US 20190340978A1 · Cha et al. · 2019 [cited by applicant]
US 20190371237A1 · Qian et al. · 2019 [cited by applicant]
US 20200082755A1 · Kim et al. · 2020 [cited by applicant]
US 20210335235A1 · Yang · 2021 [cited by examiner]
CN 107316613 · 2017 [cited by applicant]
CN 108154846 · 2018 [cited by applicant]
CN 109427301 · 2019 [cited by applicant]
KR 1020050090666 · 2005 [cited by applicant]
KR 101151609 · 2012 [cited by applicant]
KR 1020140092574 · 2014 [cited by applicant]
KR 1020160092115 · 2016 [cited by applicant]
KR 1020190010058 · 2019 [cited by applicant]
KR 1020190033678 · 2019 [cited by applicant]
KR 102004359 · 2019 [cited by applicant]
KR 1020190116597 · 2019 [cited by applicant]
KR 1020190126965 · 2019 [cited by applicant]
KR 1020190138586 · 2019 [cited by applicant]
English Translation of CN 107316613 (Year: 2017). [cited by examiner]
Cited By (1)
US 12,706,026