Hybrid victim cache and write miss buffer with fence operation
A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.
1. A system, comprising:
a first sub-cache; and
a second sub-cache, comprising:
a set of cache lines configured to store data evicted from the first sub-cache; and
a memory configured to store a set of eviction tags each corresponding to a respective cache line of the set of cache lines,
wherein the second sub-cache is configured to:
receive a first write memory command for a memory address, the first write memory command associated with a first eviction tag;
store first data associated with the first write memory command in a cache line of the second sub-cache;
store the first eviction tag in the memory;
receive a second write memory command for the cache line, the second write memory command associated with a second eviction tag; and
merge the second eviction tag with the first eviction tag to generate a merged eviction tag.
2. The system of claim 1 , wherein the first eviction tag is same as the second eviction tag, and wherein the merged eviction tag is same as the first eviction tag.
3. The system of claim 1 , wherein the first eviction tag is different from the second eviction tag, and wherein the merged eviction tag includes both the first and second eviction tags.
4. The system of claim 3 , wherein the second sub-cache is configured to evict the first data of the cache line based on the first eviction tag or the second eviction tag.
5. The system of claim 1 , wherein the first and second eviction tags are represented by respective values of a first bit field and a second bit field in an entry of the memory.
6. The system of claim 5 , wherein the entry comprises one or more additional fields configured to store values indicating modified, exclusive, shared, and invalid (MESI) states of the first data of the cache line.
7. The system of claim 6 , wherein the one or more additional fields comprises a field storing a value that indicates whether the first data is associated with a write memory command that misses in the first sub-cache.
8. A method, comprising:
receiving, by a caching system, a first write memory command for a memory address, wherein the caching system includes a first sub-cache and a second sub-cache, wherein the second sub-cache includes a set of cache lines and a memory, wherein the set of cache lines stores data evicted from the first sub-cache, wherein the memory stores a set of eviction tags each corresponding to a respective cache line of the set of cache lines, and wherein the first write memory command is associated with a first eviction tag;
storing, by the second sub-cache, first data associated with the first write memory command in a cache line of the second sub-cache;
storing, by the second sub-cache, the first eviction tag in the memory;
receiving, by the caching system, a second write memory command for the cache line, wherein the second write memory command is associated with a second eviction tag; and
merging, by the second sub-cache, the second eviction tag with the first eviction tag to generate a merged eviction tag.
9. The method of claim 8 , wherein the first eviction tag is same as the second eviction tag, and wherein the merged eviction tag is same as the first eviction tag.
10. The method of claim 8 , wherein the first eviction tag is different from the second eviction tag, and wherein the merged eviction tag includes both the first and second eviction tags.
11. The method of claim 10 , further comprising evicting the first data of the cache line from the second sub-cache based on the first eviction tag or the second eviction tag.
12. The method of claim 8 , wherein the first and second eviction tags are represented by respective values of a first bit field and a second bit field in an entry of the memory.
13. The method of claim 12 , wherein the entry comprises one or more additional fields storing values that indicate modified, exclusive, shared, and invalid (MESI) states of the first data of the cache line.
14. The method of claim 13 , wherein the one or more additional fields comprises a field storing a value that indicates whether the first data is associated with a write memory command that misses in the first sub-cache.
15. A device, comprising:
a processor;
a first sub-cache coupled to the processor; and
a second sub-cache, comprising:
a set of cache lines configured to store data evicted from the first sub-cache; and
a memory configured to store a set of eviction tags each corresponding to a respective cache line of the set of cache lines,
wherein the second sub-cache is configured to:
receive a first write memory command for a memory address, the first write memory command associated with a first eviction tag;
store first data associated with the first write memory command in a cache line of the second sub-cache;
store the first eviction tag in the memory;
receive a second write memory command for the cache line, the second write memory command associated with a second eviction tag; and
merge the second eviction tag with the first eviction tag to generate a merged eviction tag.
16. The device of claim 15 , wherein the second sub-cache is configured to evict the first data of the cache line based on the merged eviction tag.
17. The device of claim 15 , wherein the first eviction tag is same as the second eviction tag, and wherein the merged eviction tag is same as the first eviction tag.
18. The device of claim 15 , wherein the first eviction tag is different from the second eviction tag, and wherein the merged eviction tag includes both the first and second eviction tags.
19. The device of claim 15 , wherein the first and second eviction tags are represented by respective values of a first bit field and a second bit field in an entry of the memory.
20. The device of claim 19 , wherein the entry comprises an additional field storing a value that indicates whether the first data is associated with a write memory command that misses in the first sub-cache.