Granted Patent B2

US 12,265,767 · App. 17/893,136 · Granted Apr 1, 2025

Inventor: Steven F. Hoover (Shrewsbury, MA)

Assignee: Steven Hoover

G06F30/327G06F30/3308G06F30/367

Abstract

Claims (30)

1. A computer-implemented method for resimulating operation of a portion of a model representing an electronic circuit, the method comprising:

processing a hardware-description-language (HDL) description of the electronic circuit to determine a first partition comprising a first representation of a first group of circuit elements of the electronic circuit;

determining that the first partition is a candidate for resimulation;

receiving, from a first HDL model corresponding to the HDL description, first simulation data corresponding to values of signals in the first partition;

based on determining that the first partition is a candidate for resimulation, storing, in a cache memory, the first simulation data;

receiving an indication of a request to resimulate the first partition;

processing, using the first simulation data, a second HDL model corresponding to the first partition to determine second simulation data; and

displaying, on a computer display, at least a portion of the second simulation data.

2. The method of claim 1 , further comprising:

receiving a second request to resimulate a second partition;

determining that at least a portion of the second simulation data corresponds to the second partition; and

processing, using the second simulation data, a third HDL model corresponding to the second partition.

3. The method of claim 1 , wherein determining that the first partition is a candidate for resimulation comprises processing a list of requested signals.

4. The method of claim 1 , wherein determining that the first partition is a candidate for resimulation comprises processing an interaction of a user with a user device.

5. A system comprising:

at least one processor; and

at least one memory including instructions that, when executed by the at least one processor, cause the system to:

process a hardware-description-language (HDL) description of an electronic circuit to determine a first partition comprising a first representation of a first group of circuit elements of the electronic circuit;

determine that the first partition is a candidate for resimulation;

receive, from a first HDL model corresponding to the HDL description, first simulation data corresponding to values of signals in the first partition;

based on determining that the first partition is a candidate for resimulation, store, in a cache memory, the first simulation data;

receive an indication of a request to resimulate the first partition;

process, using the first simulation data, a second HDL model corresponding to the first partition to determine second simulation data; and

display, on a computer display, at least a portion of the second simulation data.

6. The system of claim 5 , the memory further including instructions that, when executed by the at least one processor, further cause the system to:

receive a second request to resimulate a second partition;

determine that at least a portion of the second simulation data corresponds to the second partition; and

process, using the second simulation data, a third HDL model corresponding to the second partition.

7. The system of claim 5 , wherein determining that the first partition is a candidate for resimulation comprises processing a list of requested signals.

8. The system of claim 5 , wherein determining that the first partition is a candidate for resimulation comprises processing an interaction of a user with a user device.

Continuity (2)

References Cited (22)