Integrated circuit verification device, integrated circuit verification method, and non-transitory computer readable medium
According to one embodiment, an integrated circuit verification device includes: a condition property information generation unit configured to generate a plurality of condition properties that have information which imposes limitations on circuit operations or input signals, based on condition statements in a code list of a design data file; an exclusion code generation unit configured to generate, from the code list, exclusion code which is proved not to be statically covered, and a first exclusion code list to which the plurality of condition properties are applied; and an exclusion code comparison unit configured to generate a second exclusion code list from a difference between the exclusion code and the first exclusion code list.
1. An integrated circuit verification device comprising:
a condition property information generation unit configured to generate a plurality of condition properties that have information which imposes limitations on circuit operations or input signals, based on condition statements in a code list of a design data file;
an exclusion code generation unit configured to generate, from the code list, exclusion code which is proved not to be statically covered, and a first exclusion code list to which the plurality of condition properties are applied; and
an exclusion code comparison unit configured to generate a second exclusion code list from a difference between the exclusion code and the first exclusion code list, wherein
the exclusion code comparison unit:
determines whether or not there is a first condition property and a second condition property in the plurality of condition properties with which at least some pieces of uncovered code in the second exclusion code list are the same as each other, and
extracts a condition property including a signal close to an input from among the first condition property and the second condition property when there is the first condition property and the second condition property.
2. The integrated circuit verification device according to claim 1 , wherein
the exclusion code is generated by performing a formal verification on the code list, and
the first exclusion code list is generated by performing, on the code list, a formal verification having the plurality of condition properties applied thereto.
3. The integrated circuit verification device according to claim 1 , further comprising:
an uncovered code information extraction unit configured to extract the code list of the design data file from a coverage database including the design data file, as uncovered code.
4. The integrated circuit verification device according to claim 3 , wherein
the condition property information generation unit generates the plurality of condition properties based on condition statements causing each piece of uncovered code extracted by the uncovered code information extraction unit.
5. The integrated circuit verification device according to claim 1 , wherein
the exclusion code comparison unit deletes the plurality of condition properties except for the extracted condition property, and deletes the exclusion code.
6. The integrated circuit verification device according to claim 1 , wherein
the exclusion code comparison unit lists the plurality of condition properties and the exclusion code.
7. The integrated circuit verification device according to claim 1 , wherein
the design data file is register transfer level source code.
8. The integrated circuit verification device according to claim 7 , wherein
a circuit description of the register transfer level source code is described in units of logic cones.
9. The integrated circuit verification device according to claim 8 , wherein
the exclusion code comparison unit selects an input-side circuit of a logic cone in the circuit description in a case where a condition property including the signal close to the input is extracted from among the first condition property and the second condition property.
10. An integrated circuit verification method comprising:
generating a plurality of condition properties that have information which imposes limitations on circuit operations or input signals, based on condition statements in a code list of a design data file;
generating from the code list, exclusion code which is proved not to be statically covered, and a first exclusion code list to which the plurality of condition properties are applied;
generating a second exclusion code list from a difference between the exclusion code and the first exclusion code list;
determining whether or not there are the plurality of condition properties with which at least some pieces of uncovered code in the second exclusion code list are the same as each other;
determining whether or not there is a first condition property and a second condition property in the plurality of condition properties;
extracting a condition property including a signal close to an input from among the first condition property and the second condition property when there is the first condition property and the second condition property; and
outputting a presentation-use condition property list and an presentation-use exclusion code list, which are sorted and listed in order of the condition properties with the largest amount of uncovered code based on the condition properties.
11. The integrated circuit verification method according to claim 10 , further comprising:
generating the exclusion code by performing a formal verification on the code list; and
generating the first exclusion code list by performing, on the code list, a formal verification having the plurality of condition properties applied thereto.
12. The integrated circuit verification method according to claim 10 , further comprising:
extracting, in an uncovered code information extraction unit, the code list of the design data file from a coverage database including the design data file, as uncovered code.
13. The integrated circuit verification method according to claim 12 , further comprising:
generating, in a condition property information generation unit, the plurality of condition properties based on condition statements causing each piece of uncovered code extracted.
14. The integrated circuit verification method according to claim 10 , further comprising:
deleting, in an exclusion code comparison unit, the plurality of condition properties except for the extracted condition property, and deleting the exclusion code.
15. The integrated circuit verification method according to claim 10 , further comprising:
listing the plurality of condition properties and the exclusion code in the exclusion code comparison unit.
16. A non-transitory computer readable medium in which a computer program is stored, the computer program being executed by a computer used in a formal verification, the computer program comprising:
generating a plurality of condition properties that have information which imposes limitations on circuit operations or input signals, based on condition statements in a code list of a design data file;
generating from the code list, exclusion code which is proved not to be statically covered, and a first exclusion code list to which the plurality of condition properties are applied;
generating a second exclusion code list from a difference between the exclusion code and the first exclusion code list;
determining whether or not there is a first condition property and a second condition property in the plurality of condition properties with which at least some pieces of uncovered code in the second exclusion code list are the same as each other;
extracting a condition property including a signal close to an input from among the first condition property and the second condition property when there is the first condition property and the second condition property; and
outputting a presentation-use condition property list and an presentation-use exclusion code list, which are sorted and listed in order of the condition properties with the largest amount of uncovered code based on the condition properties.
17. The non-transitory computer readable medium in which the computer program is stored according to claim 16 , the computer program further comprising:
generating the exclusion code by performing a formal verification on the code list; and
generating the first exclusion code list by performing, on the code list, a formal verification having the plurality of condition properties applied thereto.
18. The non-transitory computer readable medium in which the computer program is stored according to claim 16 , the computer program further comprising:
extracting, in an uncovered code information extraction unit, the code list of the design data file from a coverage database including the design data file, as uncovered code.
19. The non-transitory computer readable medium in which the computer program is stored according to claim 18 , the computer program further comprising:
generating, in a condition property information generation unit, the plurality of condition properties based on condition statements causing each piece of uncovered code extracted.
20. The non-transitory computer readable medium in which the computer program is stored according to claim 16 , the computer program further comprising:
deleting, in an exclusion code comparison unit, the plurality of condition properties except for the extracted condition property, and deleting the exclusion code.