Method and apparatus for electromigration evaluation

1. A method, comprising:

providing an active area in an integrated circuit design layout;

grouping the active area into a first region and a second region;

calculating a first self-heating temperature of the first region of the active area;

calculating a second self-heating temperature of the second region of the active area;

determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature; and

generating a semiconductor device based on the integrated circuit design layout passing the EM evaluation,

wherein a height of the first region of the active area is different from a height of the second region of the active area.

2. The method of claim 1 , wherein the first region and the second region of the active area include the same number of polysilicon gates disposed thereon.

3. The method of claim 2 , further comprising grouping the active area into a third region, wherein the third region and the first region include different numbers of polysilicon gates disposed thereon.

4. The method of claim 3 , wherein the third region is disposed at or adjacent to an edge of the active area.

5. The method of claim 1 , further comprising grouping the active area into a third region, wherein the first region and the second region include the same width, and a width of the third region is different from the width of the first region or the second region.

6. The method of claim 5 , wherein the third region is disposed at or adjacent to an edge of the active area.

7. The method of claim 1 , wherein the first region includes a first heat generating structure and the second region includes a second heat generating structure.

8. The method of claim 1 , wherein the first region includes a first heat generating structure and the second region excludes any heat generating structure.

9. The method of claim 1 , further comprising:

identifying a heat sensitive structure in the integrated circuit design layout, wherein the heat sensitive structure is proximate to the active area;

calculating a third self-heating temperature of the heat sensitive structure; and

evaluating an evaluation temperature of the heat sensitive structure based on the first self-heating temperature, the second self-heating temperature, and the third self-heating temperature.

10. The method of claim 9 , wherein determining the Electromigration (EM) evaluation comprises:

verifying that the heat sensitive structure passes the EM evaluation by comparing the evaluation temperature with a predetermined temperature.

11. The method of claim 9 , wherein the heat sensitive structure comprises a conductive line.

12. A method, comprising:

providing an active area in an integrated circuit design layout;

grouping the active area into a first region and a second region, wherein a height of the first region of the active area is different from a height of the second region of the active area, wherein the first region includes a first plurality of the polysilicon gates and the second region includes a second plurality of the poly silicon gates;

calculating a first self-heating temperature of the first region of the active area based on an individual self-heating temperature of each of the first plurality of polysilicon gates;

calculating a second self-heating temperature of the second region of the active area based on an individual self-heating temperature of each of the second plurality of polysilicon gates;

determining an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature; and

generating a semiconductor device based on the integrated circuit design layout passing the EM evaluation.

13. The method of claim 12 , wherein a number of the first plurality of polysilicon gates is identical to a number of the second plurality of polysilicon gates.

14. The method of claim 12 , further comprising grouping the active area into a third region, wherein the first region and the second region include the same width, and a width of the third region is different from the width of the first region or the second region.

15. The method of claim 14 , wherein the third region is disposed at or adjacent to an edge of the active area.

16. The method of claim 12 , wherein the first region includes a first heat generating structure and the second region includes a second heat generating structure.

17. The method of claim 12 , further comprising:

identifying a heat sensitive structure in the integrated circuit design layout, wherein the heat sensitive structure is proximate to the active area;

calculating a third self-heating temperature of the heat sensitive structure; and

evaluating an evaluation temperature of the heat sensitive structure based on the first self-heating temperature, the second self-heating temperature, and the third self-heating temperature.

18. The method of claim 17 , wherein determining the Electromigration (EM) evaluation comprises:

verifying that the heat sensitive structure passes the EM evaluation by comparing the evaluation temperature with a predetermined temperature.

19. The method of claim 17 , wherein the heat sensitive structure comprises a conductive line.

20. An apparatus, comprising:

at least one non-transitory computer-readable medium having stored thereon computer-executable instructions; and

at least one processor coupled to the at least one non-transitory computer-readable medium, wherein the computer-executable instructions cause the at least one processor to:

group an active area of an integrated circuit design layout into a first region and a second region, wherein a height of the first region of the active area is different from a height of the second region of the active area;

calculate a first self-heating temperature of the first region of the active area;

calculate a second self-heating temperature of the second region of the active area;

determine an Electromigration (EM) evaluation based on the first self-heating temperature and the second self-heating temperature; and

generate a tape out file for manufacturing a semiconductor device according to the integrated circuit design layout passing the EM evaluation.