Re-triggering wake-up to handle time skew between scalar and vector sides
A method for re-triggering wakeup to handle time skew between a scalar operation and a vector operation is provided. The method includes: initiating, before a Load-Store (LST) pipeline completes an execution of a load operation corresponding to a vector micro-operation (uop) dispatched to a baler issue queue, a respective load operation in a Load (LD) pipeline corresponding to the vector uop; triggering a speculative wakeup from the LD pipeline during an execution of the respective load operation; triggering a second wakeup corresponding to the speculative wakeup from the LD pipeline; and waking up, based on the second wakeup, the vector micro-operation in the baler issue queue of the baler unit.
1. A method for re-triggering wakeup to handle time skew between a scalar operation and a vector operation, comprising:
initiating, before a Load-Store (LST) pipeline completes an execution of a load operation corresponding to a vector micro-operation (uop) dispatched to a baler issue queue, a respective load operation in a Load (LD) pipeline corresponding to the vector uop;
triggering a speculative wakeup from the LD pipeline during an execution of the respective load operation;
triggering a second wakeup corresponding to the speculative wakeup from the LD pipeline; and
waking up, based on the second wakeup, the vector uop in the baler issue queue of the baler unit.
2. The method of claim 1 , wherein:
the LD pipeline includes at least a load read (LDR) stage, a load forwarding (LDF) stage, and a load data write back (LDWB) stage; and
triggering the speculative wakeup from the LD pipeline occurs during the LDR stage.
3. The method of claim 1 , wherein:
the LD pipeline includes at least a LDR stage, a LDF stage, and a LDWB stage; and
triggering the speculative wakeup from the LD pipeline occurs during the LDF stage.
4. The method of claim 2 , further comprising:
transmitting, from the baler unit, a first request to a physical readiness array (PRA) of a load transpose buffer of the baler unit to track a readiness of data derived from the execution of the corresponding load operation;
not responding, by the PRA, to the first request; and
storing a status of the first request.
5. The method of claim 3 , further comprising:
transmitting, from the baler unit, a first request to a physical readiness array (PRA) of a load transpose buffer of the baler unit to track a readiness of a data derived from the execution of the respective load operation; and
not responding, by the PRA, to the first request; and
storing a status of the first request.
6. The method of claim 4 , wherein the second wakeup corresponding to the speculative wakeup from the LD pipeline is triggered after storing the status of the first request.
7. The method of claim 5 , wherein the second wakeup corresponding to the speculative wakeup from the LD pipeline is triggered after storing the status of the first request.
8. A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising:
a processor including circuitry configured to:
initiate, before a Load-Store (LST) pipeline completes an execution of a load operation corresponding to a vector micro-operation (uop) dispatched to a baler issue queue, a respective load operation in a Load (LD) pipeline corresponding to the vector uop;
trigger a speculative wakeup from the LD pipeline during an execution of the respective load operation;
trigger a second wakeup corresponding to the speculative wakeup from the LD pipeline; and
wake up, based on the second wakeup, the vector uop in the baler issue queue of the baler unit.
9. The non-transitory computer readable medium of claim 8 , wherein:
triggering the speculative wakeup from the LD pipeline occurs during the LDR stage.
10. The non-transitory computer readable medium of claim 8 , wherein:
the LD pipeline includes at least a LDR stage, a LDF stage, and a LDWB stage; and
triggering the speculative wakeup from the LD pipeline occurs during the LDF stage.
11. The non-transitory computer readable medium of claim 9 , wherein the processor is further configured to:
transmit, from the baler unit, a first request to a physical readiness array (PRA) of a load transpose buffer of the baler unit to track a readiness of data derived from the execution of the respective load operation;
not respond, by the PRA, to the first request; and
store a status of the first request in an internal register of the processor.
12. The non-transitory computer readable medium of claim 10 , wherein the processor is further configured to:
transmit, from the baler unit, a first request to a physical readiness array (PRA) of a load transpose buffer of the baler unit to track a readiness of a data derived from the execution of the respective load operation; and
not respond, by the PRA, to the first request; and
store a status of the first request in an internal register of the processor.
13. The non-transitory computer readable medium of claim 11 , wherein the second wakeup corresponding to the speculative wakeup from the LD pipeline is triggered after storing the status of the first request.
14. The non-transitory computer readable medium of claim 12 , wherein the second wakeup corresponding to the speculative wakeup from the LD pipeline is triggered after storing the status of the first request.
15. The non-transitory computer readable medium of claim 12 , wherein the processor is further configured to:
generate an entry number from a claimed freelist such that a respective uop at LDR can index a corresponding Load Transpose Buffer (LTB) entry.
16. An integrated circuit comprising:
a baler unit comprising a baler issue queue;
a vector processing unit;
a Load-Store unit (LSU) comprising a Load-Store (LST) pipeline and a Load (LD) pipeline; and
a processor configured to:
initiate, before a Load-Store (LST) pipeline completes an execution of a load operation corresponding to a vector micro-operation (uop) dispatched to a baler issue queue, a respective load operation in a Load (LD) pipeline corresponding to the vector uop;
trigger a speculative wakeup from the LD pipeline during an execution of the respective load operation;
trigger a second wakeup corresponding to the speculative wakeup from the LD pipeline; and
wake up, based on the second wakeup, the vector micro-operation in the baler issue queue of the baler unit.
17. The integrated circuit of claim 16 , wherein:
the LD pipeline includes at least a load read (LDR) stage, a load forwarding (LDF) stage, and a load data write back (LDWB) stage; and
triggering the speculative wakeup from the LD pipeline occurs during the LDR stage or the LDF stage.
18. The integrated circuit of claim 17 , wherein:
the baler unit further comprises a load transpose buffer that includes a physical readiness array (PRA);
the processor is further configured to:
transmit, from the baler unit, a first request to the PRA of the load transpose buffer of the baler unit to track a readiness of data derived from the execution of the respective load operation;
not respond, by the PRA, to the first request; and
store a status of the first request in an internal register of the processor.
19. The integrated circuit of claim 18 , wherein the second wakeup corresponding to the speculative wakeup from the LD pipeline is triggered after storing the status of the first request.
20. The integrated circuit of claim 19 , wherein the processor is further configured to:
generate an entry number from a claimed freelist such that a respective uop at LDR can index a corresponding Load Transpose Buffer (LTB) entry.