Three-dimensional NAND memory and fabrication method thereof
The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes sequentially forming a first and a second dielectric stacks on a substrate. The first dielectric stack includes a first and a second dielectric layers alternatingly stacked in a first direction perpendicular to the substrate. The second dielectric stack comprises a third and a fourth dielectric layers stacked in the first direction. The method further includes forming an etch-stop layer on the second dielectric stack and forming a gate line slit (GLS) trench spacer to cover a sidewall of the etch-stop layer. The method further includes replacing the fourth and the second dielectric layers with conductive layers through a GLS opening to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first dielectric stack on a substrate, wherein the first dielectric stack comprises a first dielectric layer and a second dielectric layer alternatingly stacked in a first direction perpendicular to the substrate;
forming a second dielectric stack on the first dielectric stack, wherein the second dielectric stack comprises a third dielectric layer and a fourth dielectric layer stacked in the first direction;
forming an etch-stop layer on the second dielectric stack:
forming a gate line slit (GLS) opening through the etch-stop laver, the second dielectric stack and the first dielectric stack; and
replacing the fourth dielectric layer and the second dielectric layer through the GLS opening with conductive layers to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.
2. The method of claim 1 , further comprising forming a first capping layer on the etch-stop layer, wherein an etch rate of the first capping layer is higher than an etch rate of the etch-stop layer.
3. The method of claim 1 , further comprising:
forming a gate line slit (GLS) trench penetrating through the etch-stop layer; and
forming a GLS trench spacer to cover a sidewall of the etch-stop layer.
4. The method of claim 3 , wherein the forming the GLS trench spacer comprises:
forming a GLS trench isolation inside the GLS trench to cover the sidewall of the etch-stop layer, wherein an etch rate of the GLS trench isolation is lower than an etch rate of the fourth dielectric layer; and
forming the GLS opening penetrating through the GLS trench isolation, the second dielectric stack and the first dielectric stack, wherein a first width of the GLS opening in the GLS trench isolation is smaller than a second width of the GLS trench.
5. The method of claim 4 , wherein the replacing the fourth dielectric layer and the second dielectric layer with the conductive layers comprises:
removing the fourth dielectric layer and the second dielectric layer through the GLS opening to form a second lateral tunnel and a first lateral tunnel, respectively; and
forming the conductive layers in the second lateral tunnel and the first lateral tunnel.
6. The method of claim 4 , further comprising:
forming a GLS isolation layer on a sidewall of the GLS opening; and
filling the GLS opening with a GLS opening filler to form a GLS.
7. The method of claim 1 , further comprising, prior to forming the second dielectric stack, forming a channel structure penetrating through the first dielectric stack, wherein the channel structure comprises:
a channel layer;
a memory film covering a sidewall of the channel layer; and
a channel top plug at a top portion of the channel structure, wherein the channel top plug is connected to the channel layer.
8. The method of claim 7 , further comprising forming a top select structure penetrating through the etch-stop layer and the second dielectric stack, wherein the top select structure comprises:
a top select channel layer;
a top select dielectric layer covering a sidewall of the top select channel layer; and
a top select plug at a top portion of the top select structure, wherein:
the top select plug is connected to the top select channel layer;
the top select channel layer is connected to the channel top plug of the channel structure; and
a second diameter at a top of the top select plug is smaller than a first diameter at a top of the channel top plug.
9. The method of claim 8 , further comprising forming a contact electrically connected to the top select structure, wherein the contact is above or on a side of the etch-stop layer farther away from the conductive layers in the TSG film stack.
10. The method of claim 8 , further comprising forming a TSG cut penetrating through the etch-stop layer and the TSGfilm stack, wherein the TSG cut is distant from the top select structure in a second direction parallel to the substrate.
11. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first dielectric stack on a substrate, wherein the first dielectric stack comprises a first dielectric layer and a second dielectric layer alternatingly stacked in a first direction perpendicular to the substrate;
forming a second dielectric stack on the first dielectric stack, wherein the second dielectric stack comprises a third dielectric layer and a fourth dielectric layer stacked in the first direction;
forming an etch-stop layer on the second dielectric stack;
forming a channel structure penetrating through the first dielectric stack, wherein the channel structure comprises:
a channel layer;
a memory film covering a sidewall of the channel layer; and
a channel top plug at a top portion of the channel structure, wherein the channel top plug is connected to the channel layer; and
replacing the fourth dielectric layer and the second dielectric layer with conductive layers to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.
12. The method of claim 11 , further comprising forming a first capping layer on the etch-stop layer, wherein an etch rate of the first capping layer is higher than an etch rate of the etch-stop layer.
13. The method of claim 11 , further comprising:
forming a gate line slit (GLS) trench penetrating through the etch-stop layer; and
forming a GLS trench spacer to cover a sidewall of the etch-stop layer.
14. The method of claim 13 , wherein the forming the GLS trench spacer comprises:
forming a GLS trench isolation inside the GLS trench to cover the sidewall of the etch-stop layer, wherein an etch rate of the GLS trench isolation is lower than an etch rate of the fourth dielectric layer; and
forming a GLS opening penetrating through the GLS trench isolation, the second dielectric stack and the first dielectric stack, wherein a first width of the GLS opening in the GLS trench isolation is smaller than a second width of the GLS trench.
15. The method of claim 14 , wherein the replacing the fourth dielectric layer and the second dielectric layer with the conductive layers comprises:
removing the fourth dielectric layer and the second dielectric layer through the GLS opening to form a second lateral tunnel and a first lateral tunnel, respectively; and
forming the conductive layers in the second lateral tunnel and the first lateral tunnel.
16. The method of claim 14 , further comprising:
forming a GLS isolation layer on a sidewall of the GLS opening; and
filling the GLS opening with a GLS opening filler to form a GLS.
17. The method of claim 11 , further comprising:
forming a top select structure penetrating through the etch-stop layer and the second dielectric stack, wherein the top select structure comprises:
a top select channel layer;
a top select dielectric layer covering a sidewall of the top select channel layer; and
a top select plug at a top portion of the top select structure, wherein:
the top select plug is connected to the top select channel layer;
the top select channel layer is connected to the channel top plug of the channel structure; and
a second diameter at a top of the top select plug is smaller than a first diameter at a top of the channel top plug.
18. The method of claim 17 , further comprising forming a contact electrically connected to the top select structure, wherein the contact is above or on a side of the etch-stop layer farther away from the conductive layers in the TSG film stack.
19. The method of claim 17 , further comprising forming a TSG cut penetrating through the etch-stop layer and the TSG film stack, wherein the TSG cut is distant from the top select structure in a second direction parallel to the substrate.
20. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first dielectric stack on a substrate, wherein the first dielectric stack comprises a first dielectric layer and a second dielectric layer alternatingly stacked in a first direction perpendicular to the substrate;
forming a second dielectric stack on the first dielectric stack, wherein the second dielectric stack comprises a third dielectric layer and a fourth dielectric layer stacked in the first direction;
forming an etch-stop layer on the second dielectric stack;
forming a first capping layer on the etch-stop layer, wherein an etch rate of the first capping layer is higher than an etch rate of the etch-stop layer; and
replacing the fourth dielectric layer and the second dielectric layer with conductive layers to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.