IP Library Granted Patent US 12,266,535
Granted Patent B2
US 12,266,535 · App. 17/642,918 · Granted Apr 1, 2025

Mask encapsulation to prevent degradation during fabrication of high aspect ratio features

Inventors: Kapu Sirish Reddy (Portland, OR); Jon Henri (West Linn, OR); Francis Sloan Roberts (Portland, OR)
Assignee: LAM RESEARH CORPORATION
H01L21/3086C23C16/26H01L21/02274H01L21/0335H01L21/0337H01L23/298
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Quick Facts
Patent No.
US 12,266,535
App. No.
17/642,918
Granted
Apr 1, 2025
Kind
B2
Abstract

A tool and method for processing substrates by encapsulating a mask to protect from degradation during an etch-back to prevent a feature liner material from pinching off an opening during deposition-etch cycles used to fabricate high aspect ratio features with very tight critical dimension control.

Claims (47)

1. A method for fabricating a feature into a semiconductor substrate, the method comprising:

(a) encapsulating with an etch-resistant material around an opening and sidewalls of a mask defining the feature nominally etched into the semiconductor substrate;

(b) depositing an amorphous carbon liner on the sidewalls of the mask and sidewalls of the feature;

(c) performing an amorphous carbon liner etch for removing excess amorphous carbon deposited around the opening or the sidewalls of the mask during the deposition of the amorphous carbon liner, the etch-resistant material preventing or mitigating etching of the around the opening and the sidewalls of the mask during the amorphous carbon liner etch; and

(d) performing a feature etch to deepen a depth of the feature into the semiconductor substrate.

2. The method of claim 1 , further comprising repeating (d) one or more times until the feature has been etched to a desired depth into the semiconductor substrate.

3. The method of claim 1 , further comprising repeating (b) and (d) each one or more times until the feature has been etched to a desired depth into the semiconductor substrate.

4. The method of claim 1 , further comprising periodically repeating (a) to replenish the etch-resistant material around the opening and the sidewalls of the mask.

5. The method of claim 1 , wherein the amorphous carbon liner is resistant to lateral etching of the feature during the feature etch.

6. The method of claim 1 , wherein the amorphous carbon liner enables a tighter critical dimension control (CD) of the feature during the feature etch relative to performing the feature etch without the amorphous carbon liner.

7. The method of claim 1 , wherein the encapsulation with the etch-resistant material enables one or more of the following:

(i) the amorphous carbon liner etch to occur for a longer period of time before degrading the mask relative to if the mask had not been encapsulated;

(ii) the amorphous carbon liner to be deposited deeper into the feature and more uniformly on the sidewalls of the feature because excess amorphous carbon deposits is removed around the opening and the sidewalls of the mask during the amorphous carbon liner etch; or

iii) the feature etch is performed deeper because the amorphous carbon liner needs to be replenished less often because it extends deeper and more uniformly on the sidewalls of the feature.

8. The method of claim 1 , wherein the mask is one of the following:

(i) an Ashable HardMask (AHM);

(ii) a carbon mask; or

(iii) a doped material.

9. The method of claim 1 , wherein the etch-resistant material is etch-resistant to chemistries used to etch amorphous carbon.

10. The method of claim 1 , wherein the etch-resistant material is one of the following:

(i) silicon nitride;

(ii) silicon oxide; or

(iii) a combination of (i) and (ii).

11. The method of claim 1 , prior to (a), further comprising:

providing a mask material onto the semiconductor substrate;

patterning the mask to define the feature; and performing a nominal etch, using the mask, the nominal etch defining the feature in the substrate prior to encapsulation of the mask.

12. A substrate processing tool, comprising:

a processing chamber;

a substrate holder for holding a substrate for processing in the processing chamber; and

a controller arranged to execute instructions for controlling processing steps within the processing chamber for processing the substrate, the controller arranged to:

(a) encapsulate with an etch-resistant material around an opening and sidewalls of a mask defining a feature nominally etched into the substrate;

(b) deposit an amorphous carbon liner on the sidewalls of the mask and sidewalls of the feature;

(c) perform an amorphous carbon liner etch for removing excess amorphous carbon deposited around the opening or the sidewalls of the mask during the deposition of the amorphous carbon liner.

13. The substrate processing tool of claim 12 , wherein the controller is further configured to repeat (b) and (c) one or more iterations to replenish the amorphous carbon liner.

14. The substrate processing tool of claim 12 , wherein the controller is further configured to repeat (a) to replenish the etch-resistant material around the opening and the sidewalls of the mask.

15. The substrate processing tool of claim 12 , wherein the controller is further configured to repeat (b) and (c) one or more cycles to achieve a desired profile of the opening and the sidewalls of the mask.

16. The substrate processing tool of claim 12 , wherein the controller is further configured to perform (b) and (c) one or more cycles to achieve a desired profile of the amorphous carbon liner.

17. The substrate processing tool of claim 16 , wherein the desired profile is characterized by:

(i) a desired uniformity of thickness of the amorphous carbon liner,

(ii) a desired depth of the amorphous carbon liner within the feature; or

(iii) both (i) and (ii).

18. The substrate processing tool of claim 12 , wherein the etch-resistant material is etch-resistant to chemistries used to etch amorphous carbon.

19. The substrate processing tool of claim 12 , wherein the etch-resistant material is one of the following:

(i) silicon nitride;

(ii) silicon oxide; or

(iii) a combination of (i) and (ii).

20. The substrate processing tool of claim 12 , wherein the controller is further configured to perform the nominal etch of the feature and one or more feature etch cycles to deepen the feature to a desired depth.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED ON REEL 59273 FRAME 339. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 5, 2025
From: REDDY, KAPU SIRISH; HENRI, JON; ROBERTS, FRANCIS SLOAN
To: LAM RESEARCH CORPORATION
Reel/Frame 073902/0199 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2022
From: REDDY, KAPU SIRISH; HENRI, JON; ROBERTS, FRANCIS SLOAN
To: LAM RESEARH CORPORATION
Reel/Frame 059273/0339 →
Continuity (2)
Provisional Application 62909073 · Oct 1, 2019
Related Publication 20220406610A1 · Dec 22, 2022
References Cited (9)
US 20070111373A1 · Ueda · 2007 [cited by applicant]
US 20080188082A1 · Chi et al. · 2008 [cited by applicant]
US 20140295668A1 · Avasarala · 2014 [cited by applicant]
US 20170125255A1 · Kakimoto et al. · 2017 [cited by applicant]
CN 104425222 · 2015 [cited by applicant]
CN 106067513A · 2016 [cited by applicant]
KR 1020090016841 · 2009 [cited by applicant]
International Search Report from International Application No. PCT/US2020/052181 dated Jan. 26, 2021. [cited by applicant]
Written Opinion from International Application No. PCT/US2020/052181 dated Jan. 26, 2021. [cited by applicant]
Cited By (1)
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