Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same
A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.
1. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first transistor located in the first region, the first transistor including:
a plurality of first channel members vertically stacked above the substrate, and
a first gate structure wrapping around each of the first channel members, the first gate structure including a first interfacial layer; and
a second transistor located in the second region, the second transistor including:
a plurality of second channel members vertically stacked above the substrate, and
a second gate structure wrapping around each of the second channel members, the second gate structure including a second interfacial layer, the second interfacial layer having a first sub-layer and a second sub-layer over the first sub-layer, the first and second sub-layers including different material compositions, and a total thickness of the first and second sub-layers being larger than a thickness of the first interfacial layer.
2. The semiconductor device of claim 1 , wherein the first region is a core region, and the second region is an input/output (I/O) region.
3. The semiconductor device of claim 1 , wherein the total thickness of the first and second sub-layers is about 30% to 50% larger than the thickness of the first interfacial layer.
4. The semiconductor device of claim 1 , wherein a weight density of the first sub-layer is less than a weight density of the second sub-layer.
5. The semiconductor device of claim 4 , wherein the weight density of the first sub-layer is about 2.55 g/cm 3 , and the weight density of the second sub-layer is about 2.65 g/cm 3 .
6. The semiconductor device of claim 1 , wherein the first sub-layer is a compound of silicon oxide and silicon.
7. The semiconductor device of claim 6 , wherein silicon in the first sub-layer is in crystalline form.
8. The semiconductor device of claim 6 , wherein silicon in the first sub-layer is in amorphous form.
9. The semiconductor device of claim 1 , wherein the first gate structure further includes a first high-k dielectric layer and the second gate structure further includes a second high-k dielectric layer, and wherein the second high-k dielectric layer includes a higher oxygen concentration than the first high-k dielectric layer.
10. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first transistor located in the first region, the first transistor including:
a plurality of first channel members vertically stacked above the substrate, and
a first gate structure wrapping around each of the first channel members, the first gate structure including a first interfacial layer and a first high-k dielectric layer over the first interfacial layer; and
a second transistor located in the second region, the second transistor including:
a plurality of second channel members vertically stacked above the substrate, and
a second gate structure wrapping around each of the second channel members, the second gate structure including a second interfacial layer and a second high-k dielectric layer over the first interfacial layer, wherein the second high-k dielectric layer includes a higher oxygen concentration than the first high-k dielectric layer, and wherein a top portion of the second high-k dielectric layer includes an alloy oxide, a middle portion of the second high-k dielectric layer includes a same metal oxide as in the first high-k dielectric layer.
11. The semiconductor device of claim 10 , wherein a thickness of the first interfacial layer is less than a thickness of the second interfacial layer.
12. The semiconductor device of claim 10 , wherein a thickness of the first channel members is larger than a thickness of the second channel members.
13. The semiconductor device of claim 10 , wherein a bottom portion of the second high-k dielectric layer includes a metal silicate.
14. The semiconductor device of claim 10 , wherein a total thickness of the first interfacial layer and the first high-k dielectric layer is smaller than a total thickness of the second interfacial layer and the second high-k dielectric layer.
15. The semiconductor device of claim 10 , wherein the alloy oxide includes hafnium and titanium.
16. A method, comprising:
forming a plurality of channel members vertically stacked over a substrate;
forming an interfacial layer wrapping around each of the channel members;
forming a high-k dielectric layer over the interfacial layer;
forming a thickness modulation layer over the high-k dielectric layer;
forming a sacrificial layer over the thickness modulation layer, the sacrificial layer filling up gaps vertically between adjacent ones of the channel members;
performing a thickness adjustment process to increase a thickness of the interfacial layer under the thickness modulation layer;
removing the thickness modulation layer; and
forming a gate electrode wrapping around the high-k dielectric layer.
17. The method of claim 16 , further comprising:
removing the sacrificial layer to release the gaps, prior to the performing of the thickness adjustment process.
18. The method of claim 16 , wherein after the performing of the thickness adjustment process, the thickness of the interfacial layer is increased about 30% to about 50%.
19. The method of claim 16 , wherein the sacrificial layer is an aluminum oxide layer.
20. The method of claim 16 , wherein the thickness modulation layer is a metal containing layer.