Semiconductor device with nano sheet transistor and method for fabricating the same
A semiconductor device comprises: a substrate including first and second buried source/drain layers; a first nano sheet stack including first nano sheets stacked in a direction vertical to the substrate; a second nano sheet stack including second nano sheets stacked in a direction vertical to the substrate; an isolation wall disposed between the first nano sheet stack and the second nano sheet stack; first gate covering portions of the first nano sheet stack and extending in a direction vertical to the substrate; second gate covering portions of the second nano sheet stack and extending in a direction vertical to the substrate; first common source/drain layers connected to end portions of the first nano sheets and to the first buried source/drain layers; and second common source/drain layers connected to end portions of the second nano sheets and to the second buried source/drain layers.
1. A method for fabricating a semiconductor device, the method comprising:
forming an alternating stack in which first semiconductor materials and second semiconductor materials are alternately disposed on a substrate;
forming a first sheet stack and a second sheet stack by etching the alternating stack;
forming an isolation wall between the first and second sheet stacks;
forming buried source/drain layers in the substrate to be aligned with the first and second sheet stacks;
removing the second semiconductor materials from the first sheet stack to form a first nano sheet stack of the first semiconductor materials;
removing the first semiconductor materials from the second sheet stack to form a second nano sheet stack of the second semiconductor materials;
forming a first gate and a second gate on the first nano sheet stack and the second nano sheet stack, respectively; and
forming first common source/drain layers and second common source/drain layers over the buried source/drain layers to be connected to the first nano sheet stack and the second nano sheet stack, respectively.
2. The method of claim 1 , wherein the first semiconductor materials of the first nano sheet stack and the second semiconductor materials of the second nano sheet stack are horizontally oriented and parallel to a surface of the substrate and are disposed in different horizontal levels.
3. The method of claim 1 , wherein the first semiconductor materials include a silicon layer and the second semiconductor materials include a silicon germanium layer.
4. The method of claim 1 , wherein the buried source/drain layers include metal silicide.
5. The method of claim 1 , wherein the first common source/drain layers and the second common source/drain layers include polysilicon.
6. The method of claim 1 , further comprising forming a first gate dielectric layer disposed between the first semiconductor materials and the first gate and including a dipole inducing layer.
7. The method of claim 6 , wherein the dipole inducing layer includes lanthanum oxide or magnesium oxide.
8. The method of claim 1 , further comprising forming a second gate dielectric layer disposed between the second semiconductor materials and the second gate,
wherein the second gate dielectric layer is dipole-free.
9. The method of claim 1 ,
wherein the first gate covers portions of the first semiconductor materials of the first nano sheet stack and extends in a direction vertical to the substrate, and
wherein the second gate covers portions of the second semiconductor materials of the second nano sheet stack and extends in a direction vertical to the substrate.
10. The method of claim 1 ,
wherein the first common source/drain layers commonly connect to the end portions of the first semiconductor materials of the first nano sheet stack and extend in a direction vertical to the substrate, and
wherein the second common source/drain layers commonly connect to the end portions of the second semiconductor materials of the second nano sheet stack and extend in a direction vertical to the substrate.
11. The method of claim 1 , wherein the first semiconductor materials and the second semiconductor materials are formed to a same height.
12. The method of claim 1 , wherein one of the first semiconductor materials and the second semiconductor materials have a lower height than the other of the first semiconductor materials and the second semiconductor materials.
13. The method of claim 12 , wherein the first semiconductor materials are formed to a first height and the second semiconductor materials are formed to a second height lower than the first height.
14. The method of claim 12 , wherein the first semiconductor materials are formed to a same height, while the second semiconductor materials are formed to different heights.
15. The method of claim 14 , wherein the second semiconductor material at the lowest level has a height greater than the second semiconductor material at the highest level.