IP Library › Granted Patent US 12,266,838
Granted Patent B2
US 12,266,838 · App. 18/018,361 · Granted Apr 1, 2025

Digital phase shift circuit and digital phase shifter

Inventor: Yusuke Uemichi (Sakura, JP)
Assignee: Fujikura Ltd.
H01P1/184H01Q3/38H03H11/16
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,266,838
App. No.
18/018,361
Granted
Apr 1, 2025
Kind
B2
Abstract

A digital phase shift circuit includes: a signal line extending in a predetermined direction; two inner lines disposed on both one side and another side of the signal line and separated a predetermined distance from the signal line; two outer lines provided at positions which are farther from the signal line than the inner lines on both the one side and the other side; a first grounding conductor electrically connected to one end of each of the inner lines and the outer lines; and a second grounding conductor electrically connected to other ends of the outer lines, and the predetermined distance is set to be less than 10 μm.

Claims (37)

1. A digital phase shift circuit comprising:

a signal line extending in a predetermined direction;

two inner lines disposed on both one side and the other side of the signal line and separated a predetermined distance from the signal line;

two outer lines provided at positions which are farther from the signal line than the inner lines on both the one side and the other side;

a first grounding conductor electrically connected to one end of each of the inner lines and the outer lines;

a second grounding conductor electrically connected to other ends of the outer lines;

a first electronic switch connected between another end of an inner line of the inner lines on the one side and the second grounding conductor;

a second electronic switch connected between another end of an inner line of the inner lines on the other side and the second grounding conductor,

a capacitor connected between the signal line and the second grounding conductor; and

a fourth electronic switch connected in series to the capacitor,

wherein the predetermined distance is set to be less than 10 μm, and

a size of an upper electrode of the capacitor is equal to or less than a width of the signal line.

2. The digital phase shift circuit according to claim 1 , wherein the predetermined distance is set to be equal to or less than 2 μm.

3. The digital phase shift circuit according to claim 1 , comprising a third electronic switch connected between the signal line and the first grounding conductor or the second grounding conductor.

4. The digital phase shift circuit according to claim 1 , wherein parts of both or one of the first grounding conductor and the second grounding conductor, which correspond to areas between the outer lines and the inner lines, are formed in a multi-layered structure.

5. The digital phase shift circuit according to claim 1 , wherein the signal line is formed in a first conductive layer, and

wherein the inner lines are formed in a second conductive layer facing the first conductive layer with an insulating layer interposed therebetween.

6. A digital phase shifter comprising:

a plurality of the digital phase shift circuits according to claim 1 connected in a cascade manner,

wherein a signal in a frequency band from a first frequency to a second frequency higher than the first frequency is shifted in phase by the plurality of digital phase shift circuits connected in a cascade manner,

wherein each of the plurality of digital phase shift circuits operates in either one operation mode of a low-delay mode in which the first electronic switch and the second electronic switch are set to a closed state and a high-delay mode in which the first electronic switch and the second electronic switch are set to an open state, and

wherein a magnitude relationship of the signal varying according to a control state of operation modes of the plurality of digital phase shift circuits differs between when a frequency of the signal is the first frequency and when the frequency of the signal is the second frequency.

7. A digital phase shifter comprising:

a plurality of the digital phase shift circuits according to claim 1 connected in a cascade manner,

wherein a signal in a frequency band from a first frequency to a second frequency higher than the first frequency is shifted in phase by the plurality of digital phase shift circuits connected in a cascade manner,

wherein each of the plurality of digital phase shift circuits operates in either one operation mode of a low-delay mode in which the first electronic switch and the second electronic switch are set to a closed state and a high-delay mode in which the first electronic switch and the second electronic switch are set to an open state, and

wherein a magnitude relationship between an amplitude of the signal when all the plurality of digital phase shift circuits are in the low-delay mode and an amplitude of the signal when all the plurality of digital phase shift circuits are in the high-delay mode differs between when a frequency of the signal is the first frequency and when the frequency of the signal is the second frequency.

8. A digital phase shift circuit comprising:

a signal line extending in a predetermined direction;

two inner lines disposed on both one side and the other side of the signal line and separated a predetermined distance from the signal line;

two outer lines provided at positions which are farther from the signal line than the inner lines on both the one side and the other side;

a first grounding conductor electrically connected to one end of each of the inner lines and the outer lines a second grounding conductor electrically connected to other ends of the outer lines;

a first electronic switch connected between another end of an inner line of the inner lines on the one side and the second grounding conductor; and

a second electronic switch connected between another end of an inner line of the inner lines on the other side of the second grounding conductor,

wherein the predetermined distance is set to be less than 10 μm,

wherein the first electronic switch and the second electronic switch are field-effect transistors, and

wherein a size of each of the field-effect transistors is equal to or greater than a length obtained by summing a width of the first grounding conductor and a width of the second grounding conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2023
From: UEMICHI, YUSUKE
To: FUJIKURA LTD.
Reel/Frame 062511/0680 →
Priority Claims (1)
JP 2021-211348 · Dec 24, 2021 · national
Continuity (1)
Related Publication 20240258670A1 · Aug 1, 2024
References Cited (18)
US 6816031B1 · Miller · 2004 [cited by applicant]
US 10009202B1 · Valdes Garcia · 2018 [cited by examiner]
US 10291282B1 · Lin · 2019 [cited by examiner]
US 20130249653A1 · Ferrari et al. · 2013 [cited by applicant]
US 20140312986A1 · Edelstein et al. · 2014 [cited by applicant]
US 20190157754A1 · Valdes Garcia · 2019 [cited by examiner]
US 20190158068A1 · Valdes Garcia · 2019 [cited by examiner]
US 20200118781A1 · Wang · 2020 [cited by examiner]
US 20220131247A1 · Li · 2022 [cited by examiner]
US 20230170851A1 · Waks · 2023 [cited by examiner]
CN 106785250A · 2017 [cited by applicant]
CN 109616723A · 2019 [cited by applicant]
CN 111326839A · 2020 [cited by applicant]
JP 2011259215A · 2011 [cited by applicant]
JP 2016158035A · 2016 [cited by applicant]
W/Japanese International Search Report dated Oct. 18, 2022, issued in counterpart International Application No. PCT/JP2022/030581. (3 pages). [cited by applicant]
Tousi et al., “A Ka-band Digitally-Controlled Phase Shifter with sub-degree Phase Precision”, 2016 IEEE Radio Frequency Integrated Circuits Symposium, pp. 356-359. Cited in Specification. (4 pages). [cited by applicant]
Sadhu Bodhisatwa et al., “A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications”, IEEE Journal of Solid-State Circuits, IEEE, USA, v… [cited by applicant]