IP Library › Granted Patent US 12,267,962
Granted Patent B2
US 12,267,962 · App. 17/981,847 · Granted Apr 1, 2025

Capacitor-wire-embedded wiring board

Inventor: Soojae Park (Anyang-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H05K1/186H01G4/01H01G4/012H01G4/28H01G4/38H01L24/16H01L25/16H05K1/119H05K1/162H05K1/181H05K1/183H01G4/008H01G4/1209H01L23/3128H01L2224/16227H01L2924/19041H01L2924/19105H01L2924/19107H05K2201/09036H05K2201/09472H05K2201/10015H05K2201/10378H05K2201/10545H05K2201/10583
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,267,962
App. No.
17/981,847
Granted
Apr 1, 2025
Kind
B2
Abstract

A wiring board includes an insulating layer having a first surface and a second surface, which are opposite to each other, upper wiring patterns on the first surface of the insulating layer, lower wiring patterns on the second surface of the insulating layer, intermediate wiring patterns, which are disposed in the insulating layer and are electrically connected to the upper wiring patterns and the lower wiring patterns, and a capacitor wire connected to corresponding wiring patterns of the upper wiring patterns, the lower wiring patterns, and the intermediate wiring patterns. The capacitor wire includes a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line.

Claims (65)

1. A wiring board, comprising:

an insulating layer having a first surface and a second surface, which are opposite to each other;

upper wiring patterns on the first surface of the insulating layer;

lower wiring patterns on the second surface of the insulating layer;

intermediate wiring patterns, which are disposed in the insulating layer and are electrically connected to the upper wiring patterns and the lower wiring patterns; and

a capacitor wire connected to corresponding wiring patterns of the upper wiring patterns, the lower wiring patterns, and the intermediate wiring patterns,

wherein the capacitor wire comprises:

a core electrode line having a wire shape;

an outer electrode line covering at least a portion of the core electrode line; and

a dielectric line interposed between the core electrode line and the outer electrode line,

wherein the outer electrode line comprises a material whose melting point is lower than a melting point of the core electrode line.

2. The wiring board of claim 1 , wherein the core electrode line comprises a first metal, and

the outer electrode line comprises a second metal different from the first metal.

3. The wiring board of claim 1 , wherein the capacitor wire has a first end portion and a second end portion, which are opposite to each other in a longitudinal direction of the core electrode line, and

at the first end portion of the capacitor wire, the core electrode line is connected to a first one of the corresponding wiring patterns by a wire bonding method, and at the second end portion of the capacitor wire, the outer electrode line is connected to a second one of the corresponding wiring patterns by the wire bonding method.

4. The wiring board of claim 1 , wherein the capacitor wire has a first end portion and a second end portion, which are opposite to each other in a longitudinal direction of the core electrode line, and

at the first end portion of the capacitor wire, the core electrode line is connected to one of the corresponding wiring patterns by a ball bonding method or a wedge bonding method.

5. The wiring board of claim 4 , wherein, at the second end portion of the capacitor wire, the outer electrode line is connected to another of the corresponding wiring patterns by a wedge bonding method.

6. The wiring board of claim 1 , further comprising a lower mask layer, which is disposed on the second surface of the insulating layer to cover the lower wiring patterns,

wherein the capacitor wire is connected to corresponding ones of the lower wiring patterns and is disposed in the lower mask layer.

7. The wiring board of claim 1 , further comprising an upper mask layer, which is disposed on the first surface of the insulating layer to cover the upper wiring patterns,

wherein the capacitor wire is connected to corresponding ones of the upper wiring patterns and is disposed in the upper mask layer.

8. The wiring board of claim 1 , wherein the capacitor wire is connected to corresponding ones of the intermediate wiring patterns and is disposed in the insulating layer.

9. The wiring board of claim 1 , wherein the insulating layer includes a cavity, and

the capacitor wire is disposed in the cavity.

10. The wiring board of claim 9 , further comprising a mold layer, which is provided to fill the cavity and to cover the capacitor wire.

11. The wiring board of claim 1 , wherein the insulating layer comprises an upper insulating layer adjacent to the first surface, and

the upper wiring patterns are embedded in the upper insulating layer.

12. The wiring board of claim 1 , wherein the insulating layer has a side surface between the first surface and the second surface, and

the capacitor wire is connected to the corresponding wiring patterns, on the side surface of the insulating layer.

13. The wiring board of claim 1 , further comprising a pillar structure disposed on the first surface of the insulating layer,

wherein the capacitor wire has a first end portion and a second end portion, which are opposite to each other in a longitudinal direction of the core electrode line,

the capacitor wire is wound around the pillar structure, and

the first end portion of the capacitor wire is connected to one of the upper wiring patterns.

14. The wiring board of claim 13 , wherein the second end portion of the capacitor wire is connected to another of the upper wiring patterns.

15. The wiring board of claim 13 , wherein the pillar structure is a conductive pillar, and

the second end portion of the capacitor wire is electrically connected to the pillar structure.

16. A wiring board, comprising:

an insulating layer having a first surface and a second surface, which are opposite to each other;

upper wiring patterns on the first surface of the insulating layer;

lower wiring patterns on the second surface of the insulating layer;

intermediate wiring patterns, which are disposed in the insulating layer and are electrically connected to the upper wiring patterns and the lower wiring patterns; and

a capacitor wire connected to corresponding wiring patterns of the upper wiring patterns, the lower wiring patterns, and the intermediate wiring patterns,

wherein the capacitor wire comprises:

a core electrode line, which has a wire shape and is extended in a longitudinal direction;

a dielectric line, which is provided to enclose an outer circumference surface of the core electrode line and is extended in the longitudinal direction; and

an outer electrode line, which is provided to enclose an outer circumference surface of the dielectric line and is extended in the longitudinal direction, and

the capacitor wire is connected to the corresponding wiring patterns by a wire bonding method.

17. The wiring board of claim 16 , wherein the capacitor wire has a first end portion and a second end portion, which are opposite to each other in the longitudinal direction, and

at the first end portion of the capacitor wire, an end portion of the core electrode line is connected to one of the corresponding wiring patterns by a ball bonding method or a wedge bonding method.

18. The wiring board of claim 17 , wherein, at the second end portion of the capacitor wire, an end portion of the outer electrode line is connected to another of the corresponding wiring patterns by a wedge bonding method.

19. The wiring board of claim 16 , further comprising at least one of an upper mask layer, which is disposed on the first surface of the insulating layer to cover the upper wiring patterns, and a lower mask layer, which is disposed on the second surface of the insulating layer to cover the lower wiring patterns,

wherein the capacitor wire is disposed in at least one of the upper mask layer, the lower mask layer, and the insulating layer.

20. A wiring board, comprising:

an insulating layer having a first surface and a second surface, which are opposite to each other;

upper wiring patterns on the first surface of the insulating layer;

lower wiring patterns on the second surface of the insulating layer;

intermediate wiring patterns, which are disposed in the insulating layer and are electrically connected to the upper wiring patterns and the lower wiring patterns; and

a capacitor wire connected to corresponding wiring patterns of the upper wiring patterns, the lower wiring patterns, and the intermediate wiring patterns,

wherein the capacitor wire comprises:

a core electrode line having a wire shape;

an outer electrode line covering at least a portion of the core electrode line; and

a dielectric line interposed between the core electrode line and the outer electrode line,

wherein the core electrode line comprises a first metal, and

wherein the outer electrode line comprises a second metal different from the first metal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2022
From: PARK, SOOJAE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 062730/0612 →
Priority Claims (1)
KR 10-2022-0033342 · Mar 17, 2022 · national
Continuity (1)
Related Publication 20230319998A1 · Oct 5, 2023
References Cited (19)
US 5828093A · Naito et al. · 1998 [cited by applicant]
US 6891258B1 · Alexander et al. · 2005 [cited by applicant]
US 7532453B2 · Yamamoto et al. · 2009 [cited by applicant]
US 7656013B2 · Horiuchi et al. · 2010 [cited by applicant]
US 7906803B2 · Shioya et al. · 2011 [cited by applicant]
US 8988857B2 · McConnell et al. · 2015 [cited by applicant]
US 9048026B2 · Ahn et al. · 2015 [cited by applicant]
US 9686862B2 · Daghighian · 2017 [cited by applicant]
US 9929722B1 · Friend et al. · 2018 [cited by applicant]
US 10290412B2 · Wolter et al. · 2019 [cited by applicant]
US 10756161B2 · Balasubramanian et al. · 2020 [cited by applicant]
US 20030085471A1 · Iijima · 2003 [cited by examiner]
US 20090277673A1 · Sohn et al. · 2009 [cited by applicant]
US 20100071944A1 · Endo · 2010 [cited by applicant]
US 20120017435A1 · Sohn et al. · 2012 [cited by applicant]
US 20150221592A1 · Verma et al. · 2015 [cited by applicant]
JP 2007184554A · 2007 [cited by applicant]
JP 2009064966A · 2009 [cited by applicant]
Examination Report dated Aug. 26, 2024 received from the Korean Patent Office for corresponding application No. KR 1020220033342. [cited by applicant]