IP Library › Granted Patent US 12,268,001
Granted Patent B2
US 12,268,001 · App. 17/736,384 · Granted Apr 1, 2025

Nonvolatile memory device

Inventors: Jung-Hwan Lee (Seoul, KR); Hyun Min Cho (Incheon, KR)
Assignee: Samsung Electronics Co., Ltd.
H10B43/27H10B43/10H10B43/30
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Quick Facts
Patent No.
US 12,268,001
App. No.
17/736,384
Granted
Apr 1, 2025
Kind
B2
Abstract

A nonvolatile memory device with improved reliability is provided. The nonvolatile memory device comprises a substrate, a mold structure including a plurality of word lines stacked on the substrate, a first word line cut region configured to cut the mold structure, a first channel structure spaced apart from the first word line cut region by a first distance, and disposed in the mold structure and the substrate, and a second channel structure spaced apart from the first word line cut region by a second distance, and disposed in the mold structure and the substrate, wherein the second distance is greater than the first distance, a first width of the first channel structure is different from a second width of the second channel structure, and a first length of the first channel structure is different from a second length of the second channel structure.

Claims (71)

1. A nonvolatile memory device comprising:

a substrate;

a mold structure including a plurality of word lines stacked on the substrate;

a first word line cut region cutting the mold structure;

a first channel structure apart from the first word line cut region by a first distance, and in the mold structure and the substrate; and

a second channel structure apart from the first word line cut region by a second distance, and in the mold structure and the substrate,

wherein the second distance is greater than the first distance,

a first width of the first channel structure is different from a second width of the second channel structure, and

a first length of the first channel structure is different from a second length of the second channel structure.

2. The nonvolatile memory device of claim 1 , wherein the first width is greater than the second width.

3. The nonvolatile memory device of claim 1 , wherein the first length is greater than the second length.

4. The nonvolatile memory device of claim 1 , further comprising:

a third channel structure apart from the first word line cut region by a third distance greater than the first and second distances and in the mold structure and the substrate.

5. The nonvolatile memory device of claim 4 , wherein

a third width of the third channel structure is different from the first width and the second width, and

a third length of the third channel structure is different from the first length and the second length.

6. The nonvolatile memory device of claim 4 , wherein

a third width of the third channel structure is the same as the second width, and

a third length of the third channel structure is the same as the second length.

7. The nonvolatile memory device of claim 4 , wherein

a third width of the third channel structure is the same as the first width, and

a third length of the third channel structure is the same as the first length.

8. The nonvolatile memory device of claim 7 , further comprising:

a fourth channel structure apart from the first word line cut region by a fourth distance greater than the third distance and in the mold structure and the substrate,

wherein a fourth width of the fourth channel structure is less than the third width, and

a fourth length of the fourth channel structure is less than the third length.

9. The nonvolatile memory device of claim 1 , further comprising:

a second word line cut region apart from the first word line cut region and cutting the mold structure; and

a third channel structure apart from the second word line cut region by a third distance and in the mold structure and the substrate.

10. The nonvolatile memory device of claim 9 , wherein

the first distance is the same as the third distance,

a third width of the third channel structure is the same as the first width, and

a third length of the third channel structure is the same as the first length.

11. The nonvolatile memory device of claim 10 , further comprising:

a first bit line connected to the first channel structure and a second bit line connected to the third channel structure,

wherein the first bit line and the second bit line are different from each other.

12. The nonvolatile memory device of claim 1 , wherein

the first channel structure and the second channel structure are arranged in a first direction from the first word line cut region,

the first and second widths are widths of the first and second channel structures in the first direction, and

the first and second lengths are lengths of the first and second channel structures in a second direction crossing the first direction.

13. The nonvolatile memory device of claim 12 , wherein the first word line cut region cuts the mold structure in a third direction crossing the first and second directions.

14. A nonvolatile memory device comprising:

a substrate;

a mold structure including a plurality of word lines stacked on the substrate;

a first word line cut region cutting the mold structure;

a second word line cut region spaced apart from the first word line cut region in a first direction, and cutting the mold structure;

a first channel structure apart from the first word line cut region by a first distance and in the mold structure and the substrate; and

a second channel structure apart from the second word line cut region by a second distance greater than the first distance and in the mold structure and the substrate,

wherein a first width of the first channel structure is different from a second width of the second channel structure, and

a first length of the first channel structure is different from a second length of the second channel structure.

15. The nonvolatile memory device of claim 14 , further comprising:

a third channel structure apart from the second word line cut region by the first distance and in the mold structure and the substrate,

wherein a third width of the third channel structure is the same as the first width, and

a third length of the third channel structure is the same as the first length.

16. The nonvolatile memory device of claim 15 , further comprising:

a first bit line coupled to the first channel structure and the second channel structure; and

a second bit line apart from the first bit line in a second direction crossing the first direction and connected to the third channel structure,

wherein the first bit lines and the second bit lines are not contiguous with each other.

17. The nonvolatile memory device of claim 14 , wherein a third distance from the first word line cut region to the second channel structure is greater than the second distance, and

a fourth distance from the second word line cut region to the first channel structure is greater than the first distance.

18. The nonvolatile memory device of claim 14 , wherein the first width is greater than the second width, and the first length is greater than the second length.

19. A nonvolatile memory device comprising:

a substrate;

a mold structure including a plurality of word lines stacked on the substrate;

a first word line cut region cutting the mold structure;

a second word line cut region apart from the first word line cut region in a first direction and cutting the mold structure;

a first channel structure apart from the first word line cut region by a first distance and in the mold structure and the substrate;

a second channel structure spaced apart from the first word line cut region by a second distance greater than the first distance, and in the mold structure and the substrate; and

a third channel structure apart from the first word line cut region by a third distance greater than the second distance, and in the mold structure and the substrate,

wherein a first length of the first channel structure is different from a second length of the second channel structure and a third length of the third channel structure.

20. The nonvolatile memory device of claim 19 , wherein the first to third channel structures are between the first and second word line cut regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2022
From: LEE, JUNG-HWAN; CHO, HYUN MIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 059877/0479 →
Priority Claims (1)
KR 10-2021-0087878 · Jul 5, 2021 · national
Continuity (1)
Related Publication 20230005954A1 · Jan 5, 2023
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