Granted Patent B2

US 12,271,674 · App. 17/656,041 · Granted Apr 8, 2025

Inventors: David Wolpert (Poughkeepsie, NY); Matthew T. Guzowski (Essex Junction, VT); Michael Hemsley Wood (Wilmington, DE); Leon Sigal (Monsey, NY)

Assignee: International Business Machines Corporation

G06F30/394G06F2119/12

Abstract

Claims (38)

1. A method comprising:

determining power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design, the power delivery network comprises power wires and power staples connecting pairs of the power wires to each other;

removing a first one or more of the power staples from the power delivery network based on the power characteristics;

routing signal wires for the logic cells after removing the first one or more of the power staples, wherein routing the signal wires includes routing a first signal wire of the signal wires in a routing track corresponding to the first one or more of the power staples;

inserting a second one or more of the power staples within the power delivery network based on routing the signal wires to generate an updated power delivery network; and

generating an updated timing model for the updated power delivery network.

2. The method of claim 1 , wherein generating the updated timing model comprises:

generating a timing offset based on the updated power delivery network; and

updating timing information for each cell within the power delivery network based on the updated timing model.

3. The method of claim 1 , wherein determining the power characteristics comprises determining a non-critical path within the circuit design, and removing the first one or more of the power staples based on the determination of the non-critical path.

4. The method of claim 1 , wherein the power wires include a first power wire, and a second power wire, wherein a first power staple and a second power staple of the power staples connect the first power wire and the second power wire, and wherein removing the first one or more of the power staples comprises removing the first power staple based on the power characteristics.

5. The method of claim 4 , wherein routing the signal wires for the logic cells after removing the first one or more of the power staples, comprises routing a first one of the signal wires within a routing track associated with the first power staple.

6. The method of claim 4 , further comprising determining that a routing track associated with the first power staple was unused when routing the signal wires for the logic cells, and reinserting the first power staple within the power delivery network.

7. A circuit design system comprising:

an analysis engine configured to:

determine power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design, the power delivery network comprises power wires and power staples connecting pairs of the power wires to each other; and

remove a first one or more of the power staples from the power delivery network based on the power characteristics; and

a routing engine configured to route signal wires for the logic cells after removing the one or more of the power staples, wherein routing the signal wires includes routing a first signal wire of the signal wires in a routing track associated with the first one or more of the power staples, wherein the analysis engine is further configured to insert a second one or more of the power staples within the power delivery network based on routing the signal wires to generate an updated power delivery network, and generate an updated timing model for the updated power delivery network.

8. The circuit design system of claim 7 , wherein determining the power characteristics comprises determining a non-critical path within the circuit design, and removing the first one or more of the power staples based on the determination of the non-critical path.

9. The circuit design system of claim 7 , wherein the power wires include a first power wire and a second power wire, wherein a first power staple of the power staples connects the first power wire and the second power wire, and wherein removing the first one or more of the power staples comprises removing the first power staple based on the power characteristics.

10. The circuit design system of claim 9 , wherein routing the signal wires for the logic cells after removing the first one or more of the power staples, comprises routing a first one of the signal wires within a routing track associated with the first power staple.

11. The circuit design system of claim 10 , wherein the analysis engine is further configured to determine that a routing track associated with the first power staple was unused when routing the signal wires for the logic cells, and reinsert the first power staple within the power delivery network.

12. The circuit design system of claim 7 , wherein generating the updated timing model comprises:

generating a timing offset based on the updated power delivery network; and

updating timing information for each cell within the power delivery network based on the updated timing model.

13. A computer program product for generating a circuit design, the computer program product comprising:

a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to:

determine power characteristics for a power delivery network of the circuit design based on logic cells of the circuit design, the power delivery network comprises power wires and power staples connecting pairs of the power wires to each other;

remove a first one or more of the power staples from the power delivery network based on the power characteristics;

route signal wires for the logic cells after removing the first one or more of the power staples, wherein routing the signal wires includes routing a first signal wire of the signal wires in a routing track associated with the first one or more of the power staples;

insert a second one or more of the power staples within the power delivery network based on routing the signal wires to generate an updated power delivery network; and

generate an updated timing model for the updated power delivery network.

14. The computer program product of claim 13 , wherein determining the power characteristics comprises determining a non-critical path within the circuit design, and removing the first one or more of the power staples based on the determination of the non-critical path.

15. The computer program product of claim 13 , wherein the power wires include a first power wire and a second power wire, wherein a first power staple and a second power staple of the power staples connect the first power wire and the second power wire, and wherein removing the first one or more of the power staples comprises removing the first power staple based on the power characteristics.

16. The computer program product of claim 15 , wherein routing the signal wires for the logic cells after removing the first one or more of the power staples, comprises routing a first one of the signal wires within a routing track associated with the first power staple.

17. The computer program product of claim 13 , wherein generating the updated timing model comprises:

generating a timing offset based on the updated power delivery network; and

updating timing information for each cell within the power delivery network based on the updated timing model.

Assignments (1)

Continuity (1)

References Cited (34)