Timing driven cell swapping

1. A method for cell swapping performed by a processor, the method comprising:

determining a location for swapping a first cell;

determining a plurality of legal positions for cell placement at the determined location;

determining a plurality of cells for placement at the plurality of legal positions;

determining a second cell from the plurality of cells, wherein determining the second cell from the plurality of cells comprises:

determining a minimum displacement for each of the plurality of cells;

determining the second cell from the plurality of cells that minimizes the minimum displacement; and

swapping the first cell with the second cell.

2. The method of claim 1 , wherein determining the location for swapping the first cell comprises:

identifying a first location associated with the first cell;

determining that the first location is not a legal location for the cell placement; and

determining, in response to determining that the first location is not the legal location, a second location comprising the legal location for the cell placement.

3. The method of claim 1 , wherein determining the plurality of legal positions at the determined location comprises determining the plurality of legal locations using a location searching window.

4. The method of claim 1 , wherein determining the plurality of cells for placement at the plurality of legal positions comprises determining a plurality of cell versions of the first cell.

5. The method of claim 4 , wherein determining the plurality of cell versions comprises determining the plurality of cell versions of a cell type associated with the first cell.

6. The method of claim 5 , wherein determining the plurality of cell versions of the cell type associated with the first cell comprises determining the plurality of cell versions, of the cell type associated with the first cell, having associated physical design constraint not violating a physical design constraint of a circuit when placed at a respective legal position.

7. The method of claim 1 , further comprising:

creating a photomask of an integrated circuit comprising the second cell; and

fabricating the integrated circuit based on the created photomask.

8. A method for cell swapping performed by a processor, the method comprising:

determining a location for swapping a first cell;

determining a plurality of legal positions for cell placement at the determined location;

determining a plurality of cells for placement at the plurality of legal positions;

determining a second cell from the plurality of cells, wherein determining the second cell from the plurality of cells comprises:

determining a maximum displacement for each of the plurality of cells;

determining the second cell from the plurality of cells that maximizes the maximum displacement; and

swapping the first cell with the second cell.

9. The method of claim 8 , further comprising:

creating a photomask of an integrated circuit comprising the second cell; and

fabricating the integrated circuit based on the created photomask.

10. The method of claim 8 , wherein determining the plurality of cells for placement at the plurality of legal positions comprises determining a plurality of cell versions of the first cell.

11. The method of claim 10 , further comprising determining the second cell comprising a cell version from the plurality of cell versions based on the maximum displacement associated with the plurality of cell versions.

12. The method of claim 10 , wherein determining the plurality of cell versions comprises determining the plurality of cell versions of a cell type associated with the first cell.

13. The method of claim 12 , wherein determining the plurality of cell versions of the cell type associated with the first cell comprises determining the plurality of cell versions, of the cell type associated with the first cell, having associated physical design constraint not violating a physical design constraint of a circuit when placed at a respective legal position.

14. The method of claim 8 , wherein determining the plurality of legal positions at the determined location comprises determining the plurality of legal locations using a location searching window.

15. A method for cell swapping performed by a processor, the method comprising:

determining a location for swapping a first cell;

determining a plurality of legal positions for cell placement at the determined location;

determining a plurality of cells for placement at the plurality of legal positions;

determining a second cell from the plurality of cells based on one of the following: a minimum displacement and a maximum displacement; and

swapping the first cell with the second cell.

16. The method of claim 15 , further comprising:

creating a photomask of an integrated circuit comprising the second cell; and

fabricating the integrated circuit based on the created photomask.

17. The method of claim 15 , wherein determining the plurality of cells for placement at the plurality of legal positions comprises determining a plurality of cell versions of the first cell.

18. The method of claim 17 , further comprising determining the second cell comprising a cell version from the plurality of cell versions based on the maximum displacement or the minimum displacement associated with the plurality of cell versions.

19. The method of claim 17 , wherein determining the plurality of cell versions comprises determining the plurality of cell versions of a cell type associated with the first cell.

20. The method of claim 19 , wherein determining the plurality of cell versions of the cell type associated with the first cell comprises determining the plurality of cell versions, of the cell type associated with the first cell, having associated physical design constraint not violating a physical design constraint of a circuit when placed at a respective legal position.