IP Library › Granted Patent US 12,271,808
Granted Patent B2
US 12,271,808 · App. 17/191,292 · Granted Apr 8, 2025

Method and apparatus with neural network operation

Inventors: Myeong Woo Kim (Suwon-si, KR); Hanwoong Jung (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
G06N3/063G06F7/50G06F7/523G06F7/5443
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,271,808
App. No.
17/191,292
Granted
Apr 8, 2025
Kind
B2
Abstract

A neural network operation apparatus includes: a receiver configured to receive a first input feature map; a controller configured to control multiplier-accumulators (MACs) included in a first MAC array; and a first operation engine comprising the first MAC array and configured to process the first input feature map based on the MACs of which operation states are controlled.

Claims (50)

1. A neural network operation apparatus, comprising:

a receiver configured to receive a first input feature map;

a controller configured to control multiplier-accumulators (MACs) included in a first MAC array by setting an operation state of one MAC in the first MAC array to an enable state and setting an operation state of remaining MACs in the first MAC array to a disable state; and

a first operation engine comprising the first MAC array and configured to process the first input feature map based on the MACs of which operation states are controlled.

2. The apparatus of claim 1 , wherein

for the processing, the first operation engine is configured to perform a depthwise convolution operation on the first input feature map.

3. The apparatus of claim 2 , wherein, for the receiving, the receiver is configured to receive a second input feature map.

4. The apparatus of claim 1 , further comprising:

a second operation engine comprising a second MAC array and configured to process a second input feature map based on the second MAC array.

5. The apparatus of claim 4 , wherein

for the controlling, the controller is configured to control the first operation engine and the second operation engine, and

the first operation engine and the second operation engine are configured to perform an elementwise sum operation of the first input feature map and the second input feature map by the first operation engine performing a multiplication and addition operation on the first input feature map and the second operation engine performing a multiplication and addition operation on the second input feature map, based on the controlling.

6. The apparatus of claim 5 , wherein

for the controlling, the controller is configured to:

set an operation state of one MAC in the first MAC array to an enable state and set an operation state of remaining MACs in the first MAC array to a disable state; and

set an operation state of one MAC in the second MAC array to an enable state and set an operation state of remaining MACs in the second MAC array to a disable state, and

the first operation engine and the second operation engine are configured to perform an elementwise sum operation of the first input feature map and the second input feature map, based on the MACs included in the first MAC array and the MACs included in the second MAC array of which operation states are controlled.

7. The apparatus of claim 1 , further comprising:

a memory including a weight buffer having a height of “1”, a width of “1”, and a predetermined length.

8. The apparatus of claim 7 , wherein a value of a weight of the weight buffer is “1”.

9. The apparatus of claim 1 , wherein operation results of the MACs included in the first MAC array are concatenated in an adder tree operation.

10. A neural network operation method, comprising:

receiving a first input feature map;

controlling operation states of multiplier-accumulators (MACs) included in a first MAC array by setting an operation state of one MAC in the first MAC array to an enable state and setting an operation state of remaining MACs in the first MAC array to a disable state; and

processing the first input feature map based on the MACs of which operation states are controlled.

11. The method of claim 10 , wherein

the processing comprises performing a depthwise convolution operation on the first input feature map.

12. The method of claim 10 , wherein the receiving comprises receiving a second input feature map.

13. The method of claim 10 , wherein

the controlling comprises controlling operation states of MACs included in a second MAC array, and

the processing comprises processing the second input feature map based on the MACs included in the second MAC array of which operation states are controlled.

14. The method of claim 13 , wherein the processing comprises performing an elementwise sum operation of the first input feature map and the second input feature map by the first MAC array performing a multiplication and addition operation on the first input feature map and the second MAC array performing a multiplication and addition operation on the second input feature map, based on the MACs included in the first MAC array and the MACs included in the second MAC array of which operation states are controlled.

15. The method of claim 14 , wherein the controlling of the MACs included in the first MAC array and the second MAC array comprises:

setting an operation state of one MAC in the first MAC array to an enable state;

setting an operation state of remaining MACs except for the one MAC in the first MAC array to a disable state;

setting an operation state of one MAC in the second MAC array to an enable state; and

setting an operation state of remaining MACs except for the one MAC in the second MAC array to a disable state.

16. The method of claim 10 , wherein a weight used for the processing of the first input feature map has a height of “1”, a width of “1”, and a predetermined length.

17. The method of claim 16 , wherein a value of the weight is “1”.

18. The method of claim 10 , wherein operation results of the MACs included in the first MAC array are concatenated in an adder tree operation.

19. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, configure the processor to perform the method of claim 10 .

20. A neural network operation apparatus, comprising:

a first multiplier-accumulator (MAC) array configured to perform a depthwise convolution operation on a first input feature map;

a second MAC array configured to perform the depthwise convolution operation on a second input feature map; and

a controller configured to, in each of the first MAC array and the second MAC array, set an operation state of one MAC to an enable state and set an operation state of remaining MACs except for the one MAC to a disable state,

wherein, based on the set operational states, the first MAC array and the second MAC array are configured to perform an elementwise sum operation of the first input feature map and the second input feature map by respectively performing the depthwise convolution operation.

21. The apparatus of claim 20 , wherein the depthwise convolution operation is performed based on weights, and a total number of the weights is equal to a total number of input channels of either of the first input feature map and the second input feature map.

22. The apparatus of claim 20 , wherein

the first input feature map and the second input feature map correspond to images, and

the first MAC array and the second MAC array are configured to generate an output feature map by the performing of the elementwise sum operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2021
From: KIM, MYEONG WOO; JUNG, HANWOONG
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 055483/0075 →
Priority Claims (1)
KR 10-2020-0130312 · Oct 8, 2020 · national
Continuity (1)
Related Publication 20220114426A1 · Apr 14, 2022
References Cited (18)
US 6081225A · Tsai · 2000 [cited by examiner]
US 9467261B2 · Papasakellariou et al. · 2016 [cited by applicant]
US 9928035B2 · Kossel · 2018 [cited by applicant]
US 10162632B1 · Farooqui et al. · 2018 [cited by applicant]
US 10621489B2 · Appuswamy et al. · 2020 [cited by applicant]
US 11176449B1 · Nez · 2021 [cited by examiner]
US 20190095795A1 · Ren et al. · 2019 [cited by applicant]
US 20190197083A1 · Chen · 2019 [cited by examiner]
US 20200026978A1 · Ovsiannikov et al. · 2020 [cited by applicant]
US 20200073636A1 · Cammarota et al. · 2020 [cited by applicant]
US 20200090030A1 · Huang et al. · 2020 [cited by applicant]
US 20210089889A1 · Gope · 2021 [cited by examiner]
CN 109948787A · 2019 [cited by applicant]
CN 110135554A · 2019 [cited by applicant]
EP 3674982A1 · 2020 [cited by examiner]
KR 1020190099931A · 2019 [cited by applicant]
Bai, Lin, Yiming Zhao, and Xinming Huang. “A CNN accelerator on FPGA using depthwise separable convolution.” [cited by applicant]
Korean Office Action issued on Dec. 23, 2024 in corresponding Korean Patent Application No., 10-2020-0130312. (2 pages in English and 5 pages in Korean). [cited by applicant]