IP Library › Granted Patent US 12,272,498
Granted Patent B2
US 12,272,498 · App. 17/503,416 · Granted Apr 8, 2025

Multilayer ceramic capacitor

Inventor: Hiroyasu Yoshida (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G4/30H01G4/012H01G4/12H01G4/232
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Quick Facts
Patent No.
US 12,272,498
App. No.
17/503,416
Granted
Apr 8, 2025
Kind
B2
Abstract

A multilayer ceramic capacitor includes a multilayer body including a laminate chip and side gap portions. The laminate chip includes an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, and outer layer portions respectively on both sides of the inner layer portion in a lamination direction. Side gap portions are on both sides of the laminate chip in a width direction. The multilayer ceramic capacitor further includes external electrodes respectively on both sides of the multilayer body in a length direction. When a thickness of one of the outer layer portions is defined as T 1 , and a thickness of one of the side gap portions is defined as W 1 , W 1 and T 1 are about 20 μm or less, and about 0.1<|(W 1 -T 1 )|/T 1 <about 0.3 is satisfied.

Claims (23)

1. A multilayer ceramic capacitor comprising:

a multilayer body including:

a laminate chip and side gap portions, the laminate chip including an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, and outer layer portions respectively on both sides of the inner layer portion in a lamination direction, and the side gap portions respectively on both sides of the laminate chip in a width direction perpendicular or substantially perpendicular to the lamination direction; and

external electrodes on both sides of the multilayer body in a length direction intersecting the lamination direction and the width direction; wherein

when a thickness of one of the outer layer portions is defined as T 1 , and a thickness of one of the side gap portions is defined as W 1 , W 1 and T 1 are about 20 μm or less, and about 0.1<| (W 1 -T 1 )|/T 1 <about 0.3 is satisfied;

the side gap portions sandwich and cover the outer layer portions in the width direction, and cover the internal electrode layers along end portions of the internal electrode layers in the width direction; and

an interface is provided between the side gap portions and the outer layer portions.

2. The multilayer ceramic capacitor according to claim 1 , wherein about 0.8<W 1 /T 1 <about 1.3 is satisfied.

3. The multilayer ceramic capacitor according to claim 1 , wherein W 1 <T 1 is satisfied.

4. The multilayer ceramic capacitor according to claim 1 , wherein a radius of curvature R of a ridge line portion between side surfaces on both sides in the width direction of the multilayer body and main surfaces on both sides in the lamination direction of the multilayer body, in a cross-section including the width direction and the lamination direction at a middle portion in the length direction of the multilayer body, has a relationship of R>T 1 .

5. The multilayer ceramic capacitor according to claim 4 , wherein a curve connecting the side surface and the main surface including the ridge line portion in the cross-section has no inflection point.

6. The multilayer ceramic capacitor according to claim 1 , wherein a surface of the multilayer body includes a diamond-like-carbon (DLC) layer or a SiO 2 layer.

7. The multilayer ceramic capacitor according to claim 1 , wherein a dimension of the multilayer body in the length direction is about 0.2 mm or more and about 10 mm or less, a dimension of the multilayer body in the width direction is about 0.1 mm or more and about 10 mm or less, and a dimension of the multilayer body in the lamination direction is about 0.1 mm or more and about 5 mm or less.

8. The multilayer ceramic capacitor according to claim 4 , wherein R is about 23 μm to about 28 μm.

9. The multilayer ceramic capacitor according to claim 1 , wherein each of the dielectric layers has a thickness of about 0.5 μm or less.

10. The multilayer ceramic capacitor according to claim 1 , wherein each of the dielectric layers includes BaTiO 3 as a main component.

11. The multilayer ceramic capacitor according to claim 10 , wherein each of the dielectric layers further includes at least one of an Mn compound, a Fe compound, a Co compound, or a Ni compound as a sub-component.

12. The multilayer ceramic capacitor according to claim 1 , wherein a number of the dielectric layers is 15 or more and 700 or less.

13. The multilayer ceramic capacitor according to claim 1 , wherein each of the internal electrode layers includes at least one of Ni, Cu, Ag, Pd, or Ag-Pd alloy.

14. The multilayer ceramic capacitor according to claim 1 , wherein each of the internal electrode layers has a thickness of about 0.5 μm to about 2.0 μm.

15. The multilayer ceramic capacitor according to claim 1 , wherein each of the side gap portions include BaTiO 3 as a main component.

16. The multilayer ceramic capacitor according to claim 15 , wherein each of side gap portions further includes Mg.

17. The multilayer ceramic capacitor according to claim 1 , wherein the side gap portions include Si, and a content of the Si is larger in a portion of the side gap portions that is farther from the inner layer portion in the width direction than in a portion of the side gap portions that is closer to the inner layer portion in the width direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2021
From: YOSHIDA, HIROYASU
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 057814/0295 →
Priority Claims (1)
JP 2020-183729 · Nov 2, 2020 · national
Continuity (1)
Related Publication 20220139631A1 · May 5, 2022
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