Method and apparatus for DV/DT controlled ramp-on in multi-semiconductor solid-state power controllers
Multi-semiconductor SSPCs that solve bus level problems affecting systems as well as controller level problems affecting individual multi-semiconductor SSPCs are disclosed. Bus level and controller level problems adversely affect multi-semiconductor SSPCs and their associated systems. The disclosed multi-semiconductor SSPCs solve both bus level and controller level problems by implementing controlled rate-change of voltage (dv/dt) ramp-on rate, to ensure that the voltage on the input bus does not collapse when a multi-semiconductor SSPC is commanded closed and that a minimum amount of power is being dissipated evenly across the switching semiconductors.
1. A method for slew rate control of a multi-semiconductor solid state power controller (SSPC), the method comprising:
measuring, by at least one sensor, a rate-change of output voltage across a load of the multi-semiconductor SSPC having at least two switching semiconductors connected, and operable, in parallel;
comparing, by at least one amplifier, the rate-change of output voltage to a set rate-change of output voltage value to generate a rate-change of voltage error signal;
receiving, by at least one controller, a current limit set point signal; and
determining a current setting signal based on at least the rate-change of voltage error signal and the current limit set point signal.
2. The method of claim 1 , wherein the step of measuring further comprises:
receiving an input voltage signal of the multi-semiconductor SSPC;
receiving an output voltage signal representing a voltage across the load of the multi-semiconductor SSPC; and
measuring, the rate-change of output voltage across the load of the multi-semiconductor SSPC based on the input voltage signal and the output voltage signal.
3. The method of claim 1 , further comprising: commonly outputting the current setting signal to each of the at least two switching semiconductors.
4. The method of claim 1 , further comprising: controlling the rate-change of output voltage based on a value of the determined current setting signal.
5. The method of claim 1 , wherein the step of comparing further comprises amplifying a difference between the rate-change of output voltage and the set rate-change of output voltage value to generate the rate-change of voltage error signal.
6. The method of claim 1 , wherein the current limit set point signal is a fixed value during operation of the multi-semiconductor SSPC.
7. The method of claim 1 , wherein the current limit set point signal can be adjusted during operation of the multi-semiconductor SSPC.
8. The method of claim 1 , further comprising: receiving a switch open/close command, wherein the step of determining the current setting signal is based on a value of the switch open/close command.
9. The method of claim 1 , wherein the current setting signal is determined by a current limit controller.
10. The method of claim 1 , wherein the current limit set point signal can be adjusted before operation of the multi-semiconductor SSPC.
11. The method of claim 1 , wherein the current limit set point signal can be adjusted after operation of the multi-semiconductor SSPC.
12. An apparatus for slew rate control of a multi-semiconductor solid state power controller (SSPC), the apparatus comprising:
a dv/dt sensor configured to measure a rate-change of output voltage across a load of the multi-semiconductor SSPC having at least two switching semiconductors connected, and operable, in parallel;
a dv/dt error amplifier configured to compare the rate-change of output voltage to a set rate-change of output voltage value to generate a rate-change of voltage error signal;
a current limit controller configured to receive a current limit set point signal and configured to determine a current setting signal based on at least the rate-change of voltage error signal and the current limit set point signal.
13. The apparatus of claim 12 , wherein the dv/dt sensor further comprises:
a first input configured to receive an input voltage signal of the multi-semiconductor SSPC; and
a second input configured to receive an output voltage signal representing a voltage across the load of the multi-semiconductor SSPC,
wherein the dv/dt sensor is further configured to measure the rate-change of output voltage across the load of the multi-semiconductor SSPC based on the input voltage signal and the output voltage signal.
14. The apparatus of claim 12 , wherein the apparatus is configured to control the rate-change of output voltage based on a value of the determined current setting signal.
15. The apparatus of claim 12 , wherein the dv/dt error amplifier is further configured to amplify a difference between the rate-change of output voltage and the set rate-change of output voltage value to generate the rate-change of voltage error signal.
16. The apparatus of claim 12 , wherein the current limit set point signal is a fixed value during operation of the multi-semiconductor SSPC.
17. The apparatus of claim 12 , wherein the current limit set point signal can be adjusted during operation of the multi-semiconductor SSPC.
18. The apparatus of claim 12 , wherein the current limit controller is further configured to receive a switch open/close command and to determine the current setting signal based on the switch open/close command.
19. The apparatus of claim 12 , wherein the current limit set point signal can be adjusted before operation of the multi-semiconductor SSPC.
20. The apparatus of claim 12 , wherein the current limit set point signal can be adjusted after operation of the multi-semiconductor SSPC.