IP Library › Granted Patent US 12,273,034
Granted Patent B2
US 12,273,034 · App. 18/090,212 · Granted Apr 8, 2025

Power converting device, power management integrated circuit, and method for controlling power converting device

Inventors: Won Suk Jang (Daejeon, KR); Tae Kyu Nam (Daejeon, KR); Young Kook Ahn (Daejeon, KR); Sang Woo Kim (Daejeon, KR); Jung Woong Park (Daejeon, KR); Tae Heon Lee (Daejeon, KR); In Ho Jeon (Daejeon, KR)
Assignee: LX SEMICON CO., LTD.
H02M3/1586H02M1/0032H02M1/088G09G2330/021H02M3/1584
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Quick Facts
Patent No.
US 12,273,034
App. No.
18/090,212
Granted
Apr 8, 2025
Kind
B2
Abstract

The present disclosure provides for sequentially turning on a plurality of power conversion modules according to the magnitude of load power at the time of driving the power conversion modules, operating power conversion modules which have already been turned on in an optimum efficiency interval, and providing increased load power through a power conversion module which has been newly turned on.

Claims (35)

1. A power converter comprising:

a first power conversion module for which a first upper current limit is set;

a second power conversion module disposed in parallel to the first power conversion module, for which a second upper current limit is set; and

a controller configured

to control the first power conversion module such that the first power conversion module supplies a first increment in load power in a first state in which the second power conversion module is turned off,

to turn on the second power conversion module when an output current of the first power conversion module reaches the first upper current limit, and

to control the second power conversion module such that the second power conversion module supplies a second increment in the load power in a second state in which the output current of the first power conversion module is maintained at the first upper current limit,

wherein the controller is configured to increase values of the first upper current limit and the second upper current limit to supply a third increment in the load power, and

wherein the controller is configured to increase the values of the first upper current limit and the second upper current limit at a same rate in response to the third increment in the load power.

2. The power converter according to claim 1 , wherein the first upper current limit is a first current value corresponding to a previously confirmed optimum efficiency range of the first power conversion module, and the second upper current limit is a second current value corresponding to a previously confirmed optimum efficiency range of the second power conversion module.

3. The power converter according to claim 1 , wherein the first power conversion module performs pulse skip control for skipping power conversion in some control periods when the first increment is equal to or less than a preset lower limit reference value.

4. The power converter according to claim 1 , wherein the first power conversion module maintains the output current of the first power conversion module as the first upper current limit through current control.

5. The power converter according to claim 1 , wherein the first upper current limit has a value different from the second upper current limit.

6. The power converter according to claim 1 , wherein the first power conversion module includes a first power semiconductor having a first size different from a second size of a second power semiconductor included in the second power conversion module.

7. The power converter according to claim 1 , wherein the controller performs interleaving control for the first power conversion module and the second power conversion module in a state in which both the first power conversion module and the second power conversion module are turned on.

8. The power converter according to claim 1 , wherein the first power conversion module and the second power conversion module operate as a buck converter using a plurality of power semiconductors connected in series between a high driving voltage and a low driving voltage.

9. A power management integrated circuit comprising:

a first module driver configured to control a duty of a first power semiconductor included in a first power conversion module for which a first upper current limit is set;

a second module driver configured to control a duty of a second power semiconductor included in a second power conversion module, for which a second upper current limit is set, disposed in parallel to the first power conversion module; and

a controller configured to control the first module driver such that the first power conversion module supplies a first increment in load power in a state in which the second power conversion module is turned off, to turn on the second power conversion module when an output current of the first power conversion module reaches a first upper current limit, and to control the second module driver such that the second power conversion module supplies a second increment in the load power in a state in which the output current of the first power conversion module is maintained as the first upper current limit,

wherein the controller is configured to increase values of the first upper current limit and the second upper current limit to supply a third increment in the load power, and

wherein the controller is configured to increase the values of the first upper current limit and the second upper current limit at a same rate in response to the third increment in the load power.

10. The power management integrated circuit according to claim 9 , wherein a size of the first power semiconductor is less than a size of the second power semiconductor.

11. The power management integrated circuit according to claim 9 , further comprising an (N−1)-th module driver configured to control an (N−1)-th power conversion module, and an N-th module driver configured to control an N-th power conversion module, N being a natural number of 3 or more,

wherein the controller turns on the N-th power conversion module when the (N−1)-th power conversion module reaches an upper power limit according to increase in the load power, and provides the increased amount of power through the N-th power conversion module.

12. The power management integrated circuit according to claim 9 , wherein the load power is supplied to a gate driver, a source driver, or a display panel of a display device.

13. The power management integrated circuit according to claim 9 , wherein, when both of the first power conversion module and the second power conversion module operate, the controller controls the first module driver and the second module driver such that turn-on times of the first power semiconductor and the second power semiconductor are different from each other.

14. A method for controlling a power converter, comprising:

turning on a first power conversion module and supplying a first increment in load power using the first power conversion module for which a first upper current limit is set;

turning on a second power conversion module when an output current of the first power conversion module reaches the first upper current limit; and

maintaining the output current of the first power conversion module as the first upper current limit and supplying a second increment in the load power using the second power conversion module for which a second upper current limit is set,

wherein the method further comprises:

increasing values of the first upper current limit and the second upper current limit to supply a third increment in the load power, and

wherein the values of the first upper current limit and the second upper current limit are increased at a same rate in response to the third increment in the load power.

15. The method according to claim 14 , wherein the first power conversion module includes a first power semiconductor having a lower duty limit value, and in the supplying the first increment in the load power using the first power conversion module, the first power conversion module performs pulse skip control for skipping power conversion in some control periods when a duty of the first power semiconductor reaches the lower duty limit value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2022
From: JANG, WON SUK; NAM, TAE KYU; AHN, YOUNG KOOK; KIM, SANG WOO; PARK, JUNG WOONG; LEE, TAE HEON; JEON, IN HO
To: LX SEMICON CO., LTD.
Reel/Frame 062248/0362 →
Priority Claims (1)
KR 10-2021-0192742 · Dec 30, 2021 · national
Continuity (1)
Related Publication 20230216416A1 · Jul 6, 2023
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