IP Library › Granted Patent US 12,273,098
Granted Patent B2
US 12,273,098 · App. 18/130,502 · Granted Apr 8, 2025

Method for operating a power transistor circuit

Inventors: Christian Fachmann (Villach, AT); Matteo-Alessandro Kutschak (Ludmannsdorf, AT); Otto Wiedenbauer (Villach, AT); Winfried Kaindl (Unterhaching, DE); Hans Weber (Villach, AT)
Assignee: Infineon Technologies Austria AG
H03K17/08122H03K17/284
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Quick Facts
Patent No.
US 12,273,098
App. No.
18/130,502
Granted
Apr 8, 2025
Kind
B2
Abstract

A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.

Claims (46)

1. A method, comprising:

switching off a power transistor circuit in an electronic circuit,

wherein the electronic circuit comprises a power source and a load circuit,

wherein the power transistor circuit is connected between the power source and the load circuit,

wherein switching off the power transistor circuit comprises operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor, and

wherein the power transistor circuit comprises a first circuit node directly connected to the power source and a second circuit node connected to the load circuit, wherein the at least one power transistor comprises a load path, and wherein the load path of the at least one power transistor is directly connected between the first and second circuit nodes.

2. The method of claim 1 , wherein the at least one power transistor comprises exactly one power transistor.

3. The method of claim 1 , wherein the at least one power transistor comprises two or more power transistors.

4. The method of claim 1 , wherein the at least one power transistor is a normally-off transistor.

5. The method of claim 1 , wherein the at least one power transistor is a normally-on transistor.

6. The method of claim 1 , wherein the at least one power transistor is a superjunction transistor.

7. The method of claim 1 , wherein the power transistor circuit comprises a first circuit node connected to the power source and a second circuit node connected to the load circuit, wherein the at least one power transistor is included in a cascode circuit, wherein the cascode circuit, in addition to the at least one power transistor, comprises a further transistor, and wherein the cascode circuit is directly connected between the first and second circuit nodes.

8. The method of claim 1 , wherein both the electronic circuit and the power transistor circuit are devoid of a clamping circuit configured to clamp a voltage across the at least one power transistor to a voltage level lower than an Avalanche breakdown voltage level of the at least one power transistor.

9. The method of claim 1 , wherein the electronic circuit includes a clamping element connected in parallel with the power transistor circuit, wherein the clamping element is configured to conduct and clamp a voltage across the power transistor circuit to a voltage level that is lower than the Avalanche breakdown voltage level of the at least one power transistor after the at least one power transistor has been operating in the Avalanche mode.

10. The method of claim 1 , wherein the power source is configured to provide a direct voltage, wherein the at least one power transistor has an Avalanche breakdown voltage level and the at least one power transistor operates in the Avalanche mode when a voltage across a load path of the at least one power transistor reaches the Avalanche breakdown voltage level, and wherein the at least one power transistor is adapted to the direct voltage such that the Avalanche breakdown voltage level is between 120% and 150% of the voltage level of the direct voltage.

11. The method of claim 1 , wherein switching off the power transistor circuit comprises applying a drive voltage with an off-level between a gate node and a source node of the least one power transistor, and wherein a polarity of the off-level is opposite to a polarity of an on-level that is configured to switch on the least one power transistor.

12. The method of claim 1 , wherein switching off the power transistor circuit comprises applying, by a drive circuit, a drive voltage with an off-level between a gate node and a source node of the least one power transistor, and wherein a resistance between an output of the drive circuit and the gate node is less than 10 ohms.

13. The method of claim 1 , wherein a switching frequency of the power transistor circuit is less than 1 Hz.

14. The method of claim 1 , wherein a time delay between switching off the power transistor circuit and again switching on the power transistor circuit is longer than 1 second.

15. A method, comprising:

switching off a power transistor circuit in an electronic circuit,

wherein the electronic circuit comprises a power source and a load circuit,

wherein the power transistor circuit is connected between the power source and the load circuit,

wherein switching off the power transistor circuit comprises operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor, and

wherein the power transistor circuit comprises a first circuit node connected to the power source and a second circuit node connected to the load circuit, wherein the at least one power transistor is included in a cascode circuit, wherein the cascode circuit, in addition to the at least one power transistor, comprises a further transistor, and wherein the cascode circuit is directly connected between the first and second circuit nodes.

16. A method, comprising:

switching off a power transistor circuit in an electronic circuit,

wherein the electronic circuit comprises a power source and a load circuit,

wherein the power transistor circuit is connected between the power source and the load circuit,

wherein switching off the power transistor circuit comprises operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor, and

wherein the electronic circuit includes a clamping element connected in parallel with the power transistor circuit, wherein the clamping element is configured to conduct and clamp a voltage across the power transistor circuit to a voltage level that is lower than the Avalanche breakdown voltage level of the at least one power transistor after the at least one power transistor has been operating in the Avalanche mode.

17. A method, comprising:

switching off a power transistor circuit in an electronic circuit,

wherein the electronic circuit comprises a power source and a load circuit,

wherein the power transistor circuit is connected between the power source and the load circuit,

wherein switching off the power transistor circuit comprises operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor, and

wherein the power source is configured to provide a direct voltage, wherein the at least one power transistor has an Avalanche breakdown voltage level and the at least one power transistor operates in the Avalanche mode when a voltage across a load path of the at least one power transistor reaches the Avalanche breakdown voltage level, and wherein the at least one power transistor is adapted to the direct voltage such that the Avalanche breakdown voltage level is between 120% and 150% of the voltage level of the direct voltage.

18. A method, comprising:

switching off a power transistor circuit in an electronic circuit,

wherein the electronic circuit comprises a power source and a load circuit,

wherein the power transistor circuit is connected between the power source and the load circuit,

wherein switching off the power transistor circuit comprises operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor, and

wherein the method further comprises one or more of the following features:

applying, by a drive circuit, a drive voltage with an off-level between a gate node and a source node of the least one power transistor for switching off the power transistor circuit, and wherein a resistance between an output of the drive circuit and the gate node is less than 10 ohms;

wherein a switching frequency of the power transistor circuit is less than 1 Hz; and

wherein a time delay between switching off the power transistor circuit and again switching on the power transistor circuit is longer than 1 second.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2023
From: FACHMANN, CHRISTIAN; WEBER, HANS; KUTSCHAK, MATTEO-ALESSANDRO; WIEDENBAUER, OTTO; KAINDL, WINFRIED
To: INFINEON TECHNOLOGIES AUSTRIA AG
Reel/Frame 063658/0315 →
Priority Claims (1)
EP 22169317 · Apr 21, 2022 · regional
Continuity (1)
Related Publication 20230344422A1 · Oct 26, 2023
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