IP Library › Granted Patent US 12,273,248
Granted Patent B2
US 12,273,248 · App. 17/585,618 · Granted Apr 8, 2025

Link-quality estimation and anomaly detection in high-speed wireline receivers

Inventors: Venugopal Balasubramonian (San Jose, CA); Lenin Kumar Patra (Dublin, CA)
Assignee: Marvell Asia Pte Ltd
H04L43/08H04L43/16H04L47/24
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,273,248
App. No.
17/585,618
Granted
Apr 8, 2025
Kind
B2
Abstract

An integrated Circuit (IC) for use in a network device includes a receiver and a Link Quality Estimation Circuit (LQEC). The receiver is configured to receive a signal over a link and to process the received signal. The LQEC is configured to predict a link quality measure indicative of communication quality over the link in the future, by analyzing at least one or more settings of circuitry of the receiver, and to initiate a responsive action depending on the predicted link quality measure.

Claims (35)

1. An Integrated Circuit (IC) for use in a network device, the IC comprising:

a receiver, which is configured to receive a signal over a link and to process the received signal; and

a Link Quality Estimation Circuit (LQEC), which is configured to run an Artificial Prediction (AI) model that predicts a link quality measure indicative of a probability that the link will fail within a future time interval having a predefined length, wherein the AI model predicts the link quality measure by analyzing at least one or more settings of circuitry of the receiver, and to initiate a responsive action depending on the predicted link quality measure.

2. The apparatus according to claim 1 , wherein the LQEC is configured to initiate the responsive action by initiating a diversion of subsequent communication, at least partially, from the link to another link.

3. The apparatus according to claim 1 , wherein, by analyzing the settings of the circuitry of the receiver over time, the LQEC is configured to predict a future value or trend of the link quality measure, and to initiate the responsive action depending on the predicted future value or trend.

4. The apparatus according to claim 1 , wherein the LQEC is configured to predict the link quality measure by jointly analyzing (i) the one or more settings of the circuitry of the receiver, and (ii) one or more parameters of the received signal.

5. The apparatus according to claim 1 , wherein the LQEC is configured to initiate the responsive action by initiating a decrease of a data rate of the signal.

6. The apparatus according to claim 1 , wherein the LQEC is configured to initiate the responsive action by initiating a change in an encoding scheme used for encoding the signal.

7. The apparatus according to claim 1 , wherein the LQEC is configured to predict the link quality measure by analyzing, over time, at least one setting of the circuitry of the receiver, selected from among:

a gain of a Clock Data Recovery (CDR) circuit;

a bandwidth of the CDR circuit;

a response of an analog equalization filter;

a setting of an Analog to Digital Converter (ADC);

tap values of a digital equalizer;

an Automatic Gain Control (AGC) setting; and

a slicer threshold.

8. The apparatus according to claim 1 , wherein the receiver is disposed in a deserializer.

9. A method for use in a network device, the method comprising:

using a receiver, receiving a signal over a link and processing the received signal;

running an Artificial Prediction (AI) model that predicts a link quality measure indicative of a probability that the link will fail within a future time interval having a predefined length, wherein the AI model predicts the link quality measure by analyzing at least one or more settings of circuitry of the receiver; and

initiating a responsive action depending on the predicted link quality measure.

10. The method according to claim 9 , wherein initiating the responsive action comprises initiating a diversion of subsequent communication, at least partially, from the link to another link.

11. The method according to claim 9 , wherein analyzing the settings of the circuitry of the receiver over time comprises predicting a future value or trend of the link quality measure, and wherein initiating the responsive action is performed depending on the predicted future value or trend.

12. The method according to claim 9 , wherein predicting the link quality measure comprises jointly analyzing (i) the one or more settings of the circuitry of the receiver, and (ii) one or more parameters of the received signal.

13. The method according to claim 9 , wherein initiating the responsive action comprises initiating a decrease of a data rate of the signal.

14. The method according to claim 9 , wherein initiating the responsive action comprises initiating a change in an encoding scheme used for encoding the signal.

15. The method according to claim 9 , wherein predicting the link quality measure comprises analyzing, over time, at least one setting of the circuitry of the receiver, selected from among:

a gain of a Clock Data Recovery (CDR) circuit;

a bandwidth of the CDR circuit;

a response of an analog equalization filter;

a setting of an Analog to Digital Converter (ADC);

tap values of a digital equalizer;

an Automatic Gain Control (AGC) setting; and

a slicer threshold.

16. The method according to claim 9 , wherein the receiver is disposed in a deserializer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: MARVELL SEMICONDUCTOR, INC.
To: MARVELL ASIA PTE LTD
Reel/Frame 071915/0736 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: BALASUBRAMONIAN, VENUGOPAL; PATRA, LENIN KUMAR
To: MARVELL SEMICONDUCTOR, INC.
Reel/Frame 072336/0357 →
Continuity (2)
Provisional Application 63143577 · Jan 29, 2021
Related Publication 20220247652A1 · Aug 4, 2022
References Cited (23)
US 6178448B1 · Gray · 2001 [cited by examiner]
US 9106462B1 · Aziz et al. · 2015 [cited by applicant]
US 9210008B2 · Rane · 2015 [cited by applicant]
US 9325537B2 · Mobin et al. · 2016 [cited by applicant]
US 10419250B1 · Taylor · 2019 [cited by applicant]
US 11381474B1 · Kumar · 2022 [cited by examiner]
US 20080155373A1 · Friedman · 2008 [cited by examiner]
US 20080285443A1 · Connolly · 2008 [cited by examiner]
US 20150124976A1 · Pedersen · 2015 [cited by examiner]
US 20160219533A1 · Sahlin et al. · 2016 [cited by applicant]
US 20160233957A1 · Guo · 2016 [cited by examiner]
US 20160328356A1 · Lesartre · 2016 [cited by examiner]
US 20190028236A1 · Tonietto · 2019 [cited by examiner]
US 20190044824A1 · Yadav · 2019 [cited by examiner]
US 20210288590A1 · Cho et al. · 2021 [cited by applicant]
Suleiman, “Model Predictive Control Equalization for High-Speed IO Links,” M.Sc. Thesis, Massachusetts Institute of Technology, pp. 1-53, Jun. 2013. [cited by applicant]
Analog Devices, Inc., “High Speed Variable Gain Amplifiers (VGAs),” MT-073 Tutorial, pp. 1-9, year 2009. [cited by applicant]
Gregor et al., “Deep AutoRegressive Networks,” Proceedings of the 31st International Conference on Machine Learning, JMLR: W&CP, vol. 32, pp. 1-9, year 2014. [cited by applicant]
Jain et al., “Structural-RNN: Deep Learning on Spatio-Temporal Graphs,” CVPR Paper, Open Access Version, pp. 5308-5317, year 2015. [cited by applicant]
Palermo, “Lecture 8: RX FIR, CTLE, DFE, & Adaptive Eq.,” ECEN720: High-Speed Links, Circuits and Systems, Analog & Mixed Signal Center, Texas, A&M University, pp. 1-49, spring 2021. [cited by applicant]
Athavale et al.: “High-Speed Serial I/O Made Simple—A Designers' Guide, with FPGA Applications,” Connectivity Solutions, Preliminary Edition 1.0, pp. 1-210, Apr. 2005. [cited by applicant]
EP Application # 22154035.4 Search Report dated Jul. 6, 2022. [cited by applicant]
EP Application # 22154035.4 Office Action dated May 13, 2024. [cited by applicant]