Selective mesh routing through non-adjacent nodes
A memory array circuit routes packet data to a destination within the array. The memory array includes memory devices arranged in a plurality of rows and columns, as well as passthrough channels connecting non-adjacent memory devices. Each of the memory devices includes a memory configured to store packet data, and a packet router configured to interface with at least one adjacent memory device of the memory array. The packet router determines a destination address for a packet, and, based on the destination address, selectively forwards the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels. A memory interface routes the packet from a source to the memory array, and selectively forwarding the packet to one of the plurality of memory devices based on the destination address.
1. A circuit, comprising:
a memory array having a plurality of memory devices arranged in a plurality of rows and columns and a plurality of passthrough channels connecting non-adjacent memory devices, each of the memory devices including:
a memory configured to store packet data, and
a packet router configured to interface with at least one non-adjacent memory device of the memory array, the packet router configured to: 1) determine a destination address for a packet, and 2) based on the destination address, selectively forward the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels, the passthrough channel being routed through an adjacent memory device located between the memory device and the non-adjacent memory device, the passthrough channel being communicatively decoupled from a memory and a packet router of the adjacent memory device; and
a memory interface configured to route the packet from a source to the memory array, the memory interface selectively forwarding the packet to one of the plurality of memory devices based on the destination address;
wherein the memory interface is further configured to append the destination address to the packet prior to forwarding the packet to the memory array, the appending including a target identifier (ID) indicating XY coordinates within the memory array for the one of the plurality of memory devices.
2. The circuit of claim 1 , wherein the packet router is further configured to forward the packet to the memory in response to determining a match between the memory device and the destination address.
3. The circuit of claim 1 , wherein the plurality of passthrough channels are integral to the plurality of memory devices.
4. The circuit of claim 1 , wherein the plurality of passthrough channels connect memory devices separated by a single memory device of the memory array.
5. The circuit of claim 1 , wherein the memory interface is further configured to identify the destination address based on a packet header of the packet, the destination address indicating one of the plurality of memory devices.
6. The circuit of claim 1 , wherein the memory interface is configured to selectively forward the packet to one of a subset of the memory devices, the subset including 1) two adjacent memory devices in a first column, and 2) two non-adjacent memory devices in a second column distinct from the first column.
7. The circuit of claim 1 , wherein each of the plurality of passthrough channels connect memory devices separated by multiple memory devices.
8. The circuit of claim 1 , further comprising a plurality of memory interfaces including the memory interface, each of the plurality of memory interfaces configured to route the packet from one or more respective sources to one of a subset of the memory devices coupled to the memory interface.
9. The circuit of claim 1 , wherein the packet router is further configured to select the non-adjacent memory device for forwarding the packet based on a history of at least one memory device to which the packet router forwarded a previous packet.
10. The circuit of claim 1 , wherein the packet router is further configured to select the non-adjacent memory device for forwarding the packet based on a location of the memory interface relative to the memory array.
11. The circuit of claim 1 , wherein the packet router is further configured to select the non-adjacent memory device for forwarding the packet based on a signal issued by the memory interface.
12. A method of routing packet data, comprising:
at a memory device of a memory array having a plurality of memory devices arranged in a plurality of rows and columns and a plurality of passthrough channels connecting non-adjacent memory devices:
determine a destination address for a packet; and
based on the destination address, selectively forward the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels, the passthrough channel being routed through an adjacent memory device located between the memory device and the non-adjacent memory device, the passthrough channel being communicatively decoupled from a memory and a packet router of the adjacent memory device; and
at a memory interface, selectively forwarding the packet to one of the plurality of memory devices based on the destination address; and
at the memory interface, appending the destination address to the packet prior to forwarding the packet to the memory array, the appending including a target identifier (ID) indicating XY coordinates within the memory array for the one of the plurality of memory devices.
13. The method of claim 12 , further comprising forwarding the packet to the memory in response to determining a match between the memory device and the destination address.
14. The method of claim 12 , wherein the plurality of passthrough channels are integral to the plurality of memory devices.
15. The method of claim 12 , wherein the plurality of passthrough channels connect memory devices separated by a single memory device of the memory array.
16. The method of claim 12 , further comprising:
identifying the destination address based on a packet header of the packet, the destination address indicating one of the plurality of memory devices.
17. The method of claim 12 , further comprising, at the memory interface, selectively forwarding the packet to one of a subset of the memory devices, the subset including 1) two adjacent memory devices in a first column, and 2) two non-adjacent memory devices in a second column distinct from the first column.
18. The method of claim 17 , further comprising, at the memory device, selecting the non-adjacent memory device for forwarding the packet based on a location of the memory interface relative to the memory array.
19. A circuit, comprising:
a node array having a plurality of node devices arranged in a plurality of rows and columns and a plurality of passthrough channels connecting non-adjacent node devices, each of the node devices including:
a processor configured to process packet data, and
a packet router configured to interface with at least one non-adjacent node device of the node array, the packet router configured to: 1) determine a destination address for a packet, and 2) based on the destination address, selectively forward the packet to the non-adjacent node device via a passthrough channel of the plurality of passthrough channels, the passthrough channel being routed through an adjacent memory device located between the memory device and the non-adjacent memory device, the passthrough channel being communicatively decoupled from a memory and a packet router of the adjacent memory device; and
an interface configured to 1) append the destination address to the packet prior to forwarding the packet to the memory array, the appending including a target identifier (ID) indicating XY coordinates within the memory array for the one of the plurality of memory devices, and 2) route the packet from a source to the node array, the interface selectively forwarding the packet to one of the plurality of node devices based on the destination address.
20. A circuit, comprising:
at a memory device of a memory array having a plurality of memory devices arranged in a plurality of rows and columns and a plurality of passthrough channels connecting non-adjacent memory devices:
means for determining a destination address for a packet; and
means for selectively forwarding, based on the destination address, the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels, the passthrough channel being routed through an adjacent memory device located between the memory device and the non-adjacent memory device, the passthrough channel being communicatively decoupled from a memory and a packet router of the adjacent memory device; and
at a memory interface, means for 1) appending the destination address to the packet prior to forwarding the packet to the memory array, the appending including a target identifier (ID) indicating XY coordinates within the memory array for the one of the plurality of memory devices, and 2) selectively forwarding the packet to one of the plurality of memory devices based on the destination address.