Memory device comprising an electrically floating body transistor and methods of using
A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
1. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells include:
a memory transistor comprising a bi-stable floating body transistor having a first body region, wherein said first body region comprises a floating body region; and
a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and
an access device comprising a second body region;
wherein said bi-stable floating body transistor and said access device are electrically connected in series;
wherein said bi-stable floating body transistor further comprises a first gate region connected to a first terminal;
wherein said access device further comprises a second gate region connected to a second terminal;
wherein said access device further comprises a bit line region connected to a third terminal;
wherein a first voltage level applied to said first terminal during write operations to both said first and second states is about the same;
wherein a second voltage level applied to said second terminal during said write operations to both said first and second states is about the same;
wherein there is a time delay between when said first voltage level is triggered and when said second voltage level is triggered; and
wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells.
2. The semiconductor memory array of claim 1 , wherein said second body region comprises a second floating body region.
3. The semiconductor memory array of claim 1 , wherein a capacitance of said first body region is different from a capacitance of said second body region.
4. The semiconductor memory array of claim 1 , wherein a length of the first gate region is less than a length of the second gate region.
5. The semiconductor memory array of claim 1 , wherein a length of the first gate region is greater than a length of the second gate region.
6. The semiconductor memory array of claim 1 , wherein a volume of the first body region is smaller than a volume of the second body region.
7. The semiconductor memory array of claim 1 , wherein a capacitance of the first gate region is different from a capacitance of the second gate region.
8. The semiconductor memory array of claim 1 , further comprising at least one dummy gate region between said memory transistor and said access device.
9. The semiconductor memory array of claim 8 , wherein a work function of said dummy gate region is higher than a work function of said first gate region.
10. The semiconductor memory array of claim 1 , wherein a third voltage level is applied to said third terminal to write said first state, and a fourth voltage level is applied to said third terminal to write said second state.
11. The semiconductor memory array of claim 1 , wherein said semiconductor memory cell is a multi-port memory cell.
12. The semiconductor memory array of claim 1 comprising a fin structure.
13. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:
a memory transistor comprising a bi-stable floating body transistor having a first body region, wherein said first body region comprises a floating body region; and
a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states; and
an access device comprising a second body region;
wherein said bi-stable floating body transistor and said access device are electrically connected in series;
wherein said bi-stable floating body transistor further comprises a first gate region connected to a first terminal;
wherein said access device further comprises a second gate region connected to a second terminal;
wherein said access device further comprises a bit line region connected to a third terminal;
wherein a first voltage level applied to said first terminal during write operations to both said first and second states is about the same;
wherein a second voltage level applied to said second terminal during said write operations to both said first and second states is about the same;
wherein there is a time delay between when said first voltage level is triggered and when said second voltage level is triggered;
wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells; and
a control circuit controlling an operation of said semiconductor memory array.
14. The integrated circuit of claim 13 , wherein said second body region comprises a second floating body region.
15. The integrated circuit of claim 13 , wherein a capacitance of said first body region is different from a capacitance of said second body region.
16. The integrated circuit of claim 13 , wherein a length of the first gate region is less than a length of the second gate region.
17. The integrated circuit of claim 13 , wherein a length of the first gate region is greater than a length of the second gate region.
18. The integrated circuit of claim 13 , wherein a volume of the first body region is smaller than a volume of the second body region.
19. The integrated circuit of claim 13 , wherein a capacitance of the first gate region is different from a capacitance of the second gate region.
20. The integrated circuit of claim 13 , further comprising at least one dummy gate region between said memory transistor and said access device.
21. The integrated circuit of claim 20 , wherein a work function of said dummy gate region is higher than a work function of said first gate region.
22. The integrated circuit of claim 13 , wherein a third voltage level is applied to said third terminal to write said first state, and a fourth voltage level is applied to said third terminal to write said second state.
23. The integrated circuit of claim 13 , wherein said semiconductor memory cell is a multi-port memory cell.
24. The integrated circuit of claim 13 comprising a fin structure.