IP Library › Granted Patent US 12,273,977
Granted Patent B2
US 12,273,977 · App. 18/338,916 · Granted Apr 8, 2025

High current, low dropout driver circuit

Inventors: Cristian Grecu (Landshut, DE); Nicola Rasera (Munich, DE); Bogdan-Eugen Matei (Bavaria-Bayern, DE); Fabio Ongaro (Unterhaching, DE)
Assignee: Apple Inc.
H05B45/397G05F1/575H03M7/165H05B45/34
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,273,977
App. No.
18/338,916
Granted
Apr 8, 2025
Kind
B2
Abstract

A high current, low dropout driver circuit is disclosed. The circuit includes a decoder configured to decode a plurality of control bits to generate a plurality of control signals, and a current source having a plurality of devices. The current source is configured to activate at least a subset of the plurality of devices using the control signals to provide a load current to a load circuit, such as a light-emitting diode (LED), using activated ones of the plurality of devices and a control voltage. A control circuit is configured to generate the control voltage based on the load current and a reference current.

Claims (41)

1. An apparatus, comprising:

a decoder configured to decode a plurality of bits to generate a plurality of control signals;

a current source including a plurality of devices, wherein the current source is configured to:

activate at least a subset of the plurality of devices using the plurality of control signals; and

provide a load current to a light-emitting diode (LED) using activated ones of the plurality of devices and a control voltage; and

a control circuit configured to generate the control voltage based on the load current and a reference current.

2. The apparatus of claim 1 , wherein the control circuit includes an equalization circuit configured to generate a copy of the load current, and a regulator circuit configured to generate the control voltage using the copy of the load current.

3. The apparatus of claim 2 , wherein the equalization circuit includes a comparator circuit configured to generate a comparison voltage corresponding to the load current, wherein the copy of the load current is generated based on the comparison voltage.

4. The apparatus of claim 3 , wherein, in generating the comparison voltage, the comparator circuit is configured to compare a first drain voltage present on a control device of the regulator circuit and a second drain voltage present on respective drain terminals of the plurality of devices.

5. The apparatus of claim 2 , wherein the regulator circuit includes:

a comparator circuit configured to generate the control voltage by comparing the copy of the load current to the reference current; and

a control device having a gate terminal coupled to receive the control voltage, wherein the control device and ones of the plurality of devices have substantially equal electrical characteristics.

6. The apparatus of claim 5 , wherein the load current is substantially equal to a current through the control device multiplied by a number of active ones of the plurality of devices.

7. The apparatus of claim 2 , wherein the equalization circuit includes a current mirror and a switch, wherein, when the switch is in a first position, the current mirror is configured to mirror current according to a first ratio, and when the switch is in a second position, the current mirror is configured to mirror current according to a second ratio.

8. The apparatus of claim 1 , wherein the decoder is configured to provide a first subset of the plurality of bits to a reference current circuit configured to generate the reference current, and a second subset of the plurality of bits to generate the plurality of control signals.

9. The apparatus of claim 1 , wherein the current source comprises an M-bit thermometric current digital-to-analog converter (IDAC) and an N-bit binary IDAC.

10. The apparatus of claim 1 , wherein the decoder is configured to use a least significant subset of the plurality of bits to generate the reference current and a most significant subset of the plurality of bits to generate the plurality of control signals.

11. A method comprising:

generating a plurality of control signals, wherein the generating comprises a decoder circuit decoding a plurality of control bits;

activating at least a subset of a plurality of devices of a current source based on the plurality of control signals;

providing a load current to a load circuit based on a control voltage provided to activated ones of the plurality of devices; and

generating, using a control circuit, the control voltage based on the load current and a reference current.

12. The method of claim 11 , further comprising:

generating, using an equalization circuit, a copy of the load current; and

generating, using a regulator circuit and the copy of the load current, the control voltage.

13. The method of claim 12 , wherein generating the copy of the load current comprises a comparator of the equalization circuit generating a comparison voltage by comparing a drain voltage on a control device of the regulator circuit to a drain voltage on activated ones of the plurality of devices.

14. The method of claim 12 , further comprising:

generating the control voltage, using a comparator in the regulator circuit, by comparing the copy of the load current to the reference current; and

providing the control voltage to a gate terminal of a control device, wherein a current through the control device is substantially equal to a current through individual ones of the plurality of devices.

15. The method of claim 12 , wherein the equalization circuit comprises a current mirror, and wherein the method further comprises changing a ratio of the current mirror.

16. The method of claim 11 , further comprising the decoder circuit providing a first subset of the plurality of the control signals to a reference current generator configured to generate the reference current, and a second subset of the plurality of control signals to control activation of ones of the plurality of devices.

17. A system comprising:

a current source configured to drive a load circuit with a load current, wherein the current source includes a plurality of devices;

a decoder circuit configured to, based on an input code, selectively activate ones of the plurality of devices; and

a control circuit configured to generate a control voltage provided to a gate terminal of a replica device and corresponding ones of the plurality of devices, wherein the control circuit is configured to generate the control voltage based on a reference current, and wherein the replica device and the plurality of devices of the current source have substantially equal electrical characteristics;

wherein the replica device is configured to generate a replica current, and wherein the current source is configured to generate the load current based on the replica current and a number of the plurality of devices that are active.

18. The system of claim 17 , wherein the control circuit comprises:

an equalization circuit, wherein the equalization circuit includes configured to generate a copy of the load current; and

a regulator circuit configured to generate the control voltage based on the copy of the load current and the reference current.

19. The system of claim 17 , wherein the decoder circuit is a thermometric decoder configured to generate a plurality of bits based on an input code, and further configured to control the reference current using a first subset of the plurality of bits and a number of active ones of the plurality of devices using a second subset of the plurality of bits.

20. The system of claim 17 , wherein the load circuit is a colored light-emitting diode (LED).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2023
From: GRECU, CRISTIAN; RASERA, NICOLA; MATEI, BOGDAN-EUGEN; ONGARO, FABIO
To: APPLE INC.
Reel/Frame 064018/0086 →
Continuity (1)
Related Publication 20240431001A1 · Dec 26, 2024
References Cited (11)
US 10349478B2 · Morales et al. · 2019 [cited by applicant]
US 10439421B2 · Jefremow et al. · 2019 [cited by applicant]
US 11847982B1 · Yang · 2023 [cited by examiner]
US 20080315778A1 · Tatsukawa · 2008 [cited by applicant]
US 20130057165A1 · Ide · 2013 [cited by examiner]
US 20130214700A1 · Barnett · 2013 [cited by applicant]
US 20210259073A1 · Hu et al. · 2021 [cited by applicant]
US 20210378066A1 · Difazio et al. · 2021 [cited by applicant]
CN 114842808A · 2022 [cited by applicant]
EP 3790360A1 · 2021 [cited by applicant]
International Search Report and Written Opinion in PCT Appl. No. PCT/US2024/032748 mailed Sep. 30, 2024, 9 pages. [cited by applicant]