Power staple avoidance for routing via reduction
Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.
1. A method for providing power staple avoidance during routing in a computing environment by one or more processors comprising:
shifting one or more transistor gates in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, wherein the circuit row is partitioned into segments based on one or more fixed objects.
2. The method of claim 1 , further including adjusting the one or more transistor gates in a circuit row following initial placement of the cell pins and power staples.
3. The method of claim 1 , further including creating row segmentation of the circuit row following initial placement of the cell pins and power staples.
4. The method of claim 1 , further including partitioning a single row into one or more segments based on one or more fixed objects.
5. The method of claim 1 , further including shifting one or more transistor gates in each row of an integrated circuit using an integer linear program (“ILP”) staple avoidance operation.
6. The method of claim 1 , further including shifting one or more transistor gates in each row of an integrated circuit using a dynamic programming staple avoidance operation.
7. The method of claim 1 , further including processing the one or more transistor gates in each row from a left to right direction.
8. A system for providing power staple avoidance during routing in a computing environment, comprising:
one or more computers with executable instructions that when executed cause the system to:
shift one or more transistor gates in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, wherein the circuit row is partitioned into segments based on one or more fixed objects.
9. The system of claim 8 , wherein the executable instructions when executed cause the system to adjust the one or more transistor gates in a circuit row following initial placement of the cell pins and power staples.
10. The system of claim 8 , wherein the executable instructions when executed cause the system to create row segmentation of the circuit row following initial placement of the cell pins and power staples.
11. The system of claim 8 , wherein the executable instructions when executed cause the system to partition a single row into one or more segments based on one or more fixed objects.
12. The system of claim 8 , wherein the executable instructions when executed cause the system to shift one or more transistor gates in each row of an integrated circuit using an integer linear program (“ILP”) staple avoidance operation.
13. The system of claim 8 , wherein the executable instructions when executed cause the system to shift one or more transistor gates in each row of an integrated circuit using a dynamic programming staple avoidance operation.
14. The system of claim 8 , wherein the executable instructions when executed cause the system to process the one or more transistor gates in each row from a left to right direction.
15. A computer program product for providing power staple avoidance during routing in a computing environment, the computer program product comprising:
one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instruction comprising:
program instructions to shift one or more transistor gates in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, wherein the circuit row is partitioned into segments based on one or more fixed objects.
16. The computer program product of claim 15 , further including program instructions to adjust the one or more transistor gates in a circuit row following initial placement of the cell pins and power staples.
17. The computer program product of claim 15 , further including program instructions to create row segmentation of the circuit row following initial placement of the cell pins and power staples.
18. The computer program product of claim 15 , further including program instructions to partition a single row into one or more segments based on one or more fixed objects.
19. The computer program product of claim 15 , further including program instructions to:
shift one or more transistor gates in each row of an integrated circuit using an integer linear program (“ILP”) staple avoidance operation; or
shift one or more transistor gates in each row of an integrated circuit using a dynamic programming staple avoidance operation.
20. The computer program product of claim 15 , further including program instructions to process the one or more transistor gates in each row from a left to right direction.