Memory device using semiconductor element
A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a plate line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the plate line of the memory cell connected to an unselected page.
1. A memory device using a semiconductor element in which a page is composed of a plurality of memory cells arrayed on a substrate in a row direction, and a plurality of pages are arrayed in a column direction to constitute a memory block,
each memory cell included in each of the pages comprising:
a semiconductor base standing on a substrate in a vertical direction relative to the substrate or extending on a substrate in a horizontal direction relative to the substrate;
a first impurity layer and a second impurity layer disposed at two ends, respectively, of the semiconductor base;
a first gate insulating layer surrounding a side surface of the semiconductor base between the first impurity layer and the second impurity layer, the first gate insulating layer being in contact with or proximate to the first impurity layer;
a second gate insulating layer surrounding the side surface of the semiconductor base, and being connected to the first gate insulating layer;
a third gate insulating layer surrounding the side surface of the semiconductor base, being connected to the second gate insulating layer, and being in contact with or proximate to the second impurity layer;
a first gate conductor layer covering the first gate insulating layer;
a second gate conductor layer covering the second gate insulating layer;
a third gate conductor layer covering the third gate insulating layer; and
a channel semiconductor layer of the semiconductor base covered with the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer, wherein:
the first impurity layer of the memory cell is connected to a source line, the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a first selection gate line, the second gate conductor layer is connected to a plate line, the third gate conductor layer is connected to a second selection gate line, and the bit line is connected to a sense amplifier circuit;
and the memory device executes:
an operation of controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity layer, and the second impurity layer to form a hole group by impact ionization inside the channel semiconductor layer, and retaining the hole group;
a page write operation of setting a voltage of the channel semiconductor layer to a first data retention voltage that is higher than a voltage of one or both of the first impurity layer and the second impurity layer;
a page erase operation of controlling a voltage applied to the first impurity layer, the second impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer to extract the hole group from one or both of the first impurity layer and the second impurity layer, and then setting the voltage of the channel semiconductor layer to a second data retention voltage that is lower than the first data retention voltage by capacitive coupling of the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer with the channel semiconductor layer; and
a page read operation of reading page data of a memory cell group selected in at least one page to the bit line, and
a voltage of zero volts or less is applied to the plate line of the memory cell connected to an unselected page among the pages.
2. The memory device using the semiconductor element according to claim 1 , wherein, during the page read operation, a ground voltage or higher voltage is applied to the plate line of the memory cell connected to a selected page.
3. The memory device using the semiconductor element according to claim 1 , wherein, during the page read operation, a refresh operation of returning the voltage of the channel semiconductor layer of a selected page to the first data retention voltage by forming the hole group by the impact ionization inside the channel semiconductor layer of the selected page is executed.
4. The memory device using the semiconductor element according to claim 1 , wherein, during the page write operation, a first N-channel metal-oxide-semiconductor (MOS) transistor region having the first gate conductor layer and a third N-channel MOS transistor region having the third gate conductor layer are operated in a linear range, and a second N-channel MOS transistor region having the second gate conductor layer is operated in a saturated range.
5. The memory device using the semiconductor element according to claim 1 , wherein the page erase operation executes:
a first operation of, after increasing a voltage of the channel semiconductor layer by capacitive coupling of the first selection gate line, the second selection gate line, and the plate line with the channel semiconductor layer, reducing a voltage of the bit line and the source line to forward bias a PN junction of the first impurity layer and the second impurity layer with the channel semiconductor layer, thereby discharging the hole group; and
a second operation of lowering the voltage of the channel semiconductor layer as a voltage of the first selection gate line, the second selection gate line, and the plate line is reduced by capacitive coupling of the first selection gate line, the second selection gate line, and the plate line with the channel semiconductor layer.
6. The memory device using the semiconductor element according to claim 1 , wherein the first selection gate line and the second selection gate line are connected.
7. The memory device using the semiconductor element according to claim 1 , wherein a total capacitance of a gate capacitance between the first gate conductor layer and the semiconductor base and a gate capacitance between the third gate conductor layer and the semiconductor base is smaller than a second gate capacitance between the second gate conductor layer and the semiconductor base.
8. The memory device using the semiconductor element according to claim 1 , wherein the impact ionization occurs inside the channel semiconductor layer in the vicinity between the second gate conductor layer and the third gate conductor layer, and the hole group is retained inside the channel semiconductor layer.
9. The memory device using the semiconductor element according to claim 1 , wherein, during a page-accumulated read operation in which at least two pages are multiple-selected, a ground voltage or higher voltage is applied to a selected plate line, and a negative voltage is applied to an unselected plate line.
10. The memory device using the semiconductor element according to claim 1 , wherein a voltage higher than or equal to a voltage applied to the plate line is applied to the first selection gate line and the second selection gate line of the memory cell connected to an unselected page among the pages.
11. The memory device using the semiconductor element according to claim 1 , wherein, in plan view, the first selection gate line, the second selection gate line, the plate line, and the source line are arranged in parallel and are arranged perpendicular to the bit line.
12. The memory device using the semiconductor element according to claim 1 , wherein, in plan view, the first selection gate line, the second selection gate line, and the plate line are arranged in parallel and are arranged perpendicular to the source line and the bit line.