Semiconductor memory devices and methods for fabricating the same
A semiconductor memory device in which performance is improved by reducing a wiring resistance is provided. The semiconductor memory device comprising an inter-wiring insulation film on a substrate, a first wiring pattern extending in a first direction, in the inter-wiring insulation film, a barrier insulation film that is on an upper surface of the inter-wiring insulation film, a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film, a memory cell electrically connected to the barrier conductive pattern and including a selection pattern and a variable resistor pattern, and a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell, wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of a portion of the memory cell that is adjacent to the barrier conductive pattern.
1. A semiconductor memory device comprising:
an inter-wiring insulation film on a substrate;
a word line extending in a first direction, in the inter-wiring insulation film;
a barrier insulation film that is on an upper surface of the inter-wiring insulation film;
a barrier conductive pattern electrically connected to the word line, in the barrier insulation film;
a memory cell electrically connected to the barrier conductive pattern and including a lower electrode pattern that is in direct contact with the barrier conductive pattern, a selection pattern on the lower electrode pattern, and a variable resistor pattern on the selection pattern; and
a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell,
wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of the lower electrode pattern and is different from a width in the second direction of the word line, and
wherein the lower electrode pattern comprises a metal, a metal nitride, or a combination thereof.
2. The semiconductor memory device of claim 1 , wherein an upper surface of the barrier insulation film and an upper surface of the barrier conductive pattern are coplanar.
3. The semiconductor memory device of claim 1 , further comprising:
a protective film that extends along an upper surface of the barrier insulation film and side surfaces of the memory cell.
4. The semiconductor memory device of claim 1 , wherein the barrier insulation film and the barrier conductive pattern are equally thick in a third direction that intersects the first direction and the second direction.
5. The semiconductor memory device of claim 1 ,
wherein the barrier insulation film includes a hole extending in a third direction intersecting an upper surface of the substrate,
wherein the barrier conductive pattern is in the hole, and
wherein an upper surface of the barrier conductive pattern is in contact with a lower surface of the memory cell.
6. The semiconductor memory device of claim 1 , wherein the width of the barrier conductive pattern in the second direction decreases toward the substrate.
7. The semiconductor memory device of claim 1 , wherein the width of the barrier conductive pattern in the second direction is smaller than the width of the memory cell in the second direction.
8. The semiconductor memory device of claim 1 ,
wherein the barrier insulation film includes at least one of silicon nitride (SiN), silicon carbonitride (SiCN), or aluminum nitride (AlN), and
wherein the barrier conductive pattern includes at least one of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), tungsten nitride (WN), tungsten carbonitride (WCN), or tungsten (W).
9. The semiconductor memory device of claim 1 , wherein the word line includes copper (Cu).
10. The semiconductor memory device of claim 9 , wherein the word line further includes:
a filling conductive film including copper (Cu); and
a barrier conductive film between the inter-wiring insulation film and the filling conductive film.
11. The semiconductor memory device of claim 1 , wherein a width of the word line in the second direction decreases toward the substrate.
12. The semiconductor memory device of claim 1 ,
wherein the variable resistor pattern is a phase change pattern in which resistance changes depending on a phase change, and
wherein the selection pattern has ovonic threshold switching (OTS) properties.
13. The semiconductor memory device of claim 1 ,
wherein the selection pattern and the variable resistor pattern are on the barrier conductive pattern, and
wherein the selection pattern is between the variable resistor pattern and the barrier conductive pattern.
14. A semiconductor memory device comprising:
an inter-wiring insulation film on a substrate;
a first wiring pattern extending in a first direction, in the inter-wiring insulation film;
a barrier insulation film that is on an upper surface of the inter-wiring insulation film;
a barrier conductive pattern electrically connected to the first wiring pattern, in the barrier insulation film;
a memory cell on the barrier conductive pattern, the memory cell including a selection pattern, a variable resistor pattern, a lower electrode pattern between the barrier conductive pattern and the selection pattern, and an upper electrode pattern on the variable resistor pattern;
a protective film that extends along an upper surface of the barrier insulation film and side surfaces of the memory cell;
a second wiring pattern that extends in a second direction intersecting the first direction, on the memory cell; and
a spacer film that is on an upper surface of the selection pattern and is between a side surface of the protective film and a side surface of the upper electrode pattern, and
wherein the lower electrode pattern comprises a metal, a metal nitride, or a combination thereof.
15. The semiconductor memory device of claim 14 , wherein:
the spacer film extends along surfaces of the variable resistor pattern, between the variable resistor pattern and the protective film.
16. The semiconductor memory device of claim 15 , wherein the spacer film does not extend along side surfaces of the selection pattern.
17. The semiconductor memory device of claim 16 , wherein a width of the selection pattern in the second direction is greater than a width of the variable resistor pattern in the second direction.
18. The semiconductor memory device of claim 14 ,
wherein the inter-wiring insulation film includes silicon oxide, and
wherein the barrier insulation film includes silicon nitride.
19. A semiconductor memory device comprising:
a first word line and a second word line that are on a substrate and each extend in a first direction, wherein the first word line is between the second word line and the substrate;
a bit line that extends in a second direction intersecting the first direction, between the first word line and the second word line;
a first barrier conductive pattern electrically connected to an upper surface of the first word line;
a first barrier insulation film that surrounds side surfaces of the first barrier conductive pattern;
a first memory cell that electrically connects the first barrier conductive pattern and the bit line, on an upper surface of the first barrier conductive pattern and an upper surface of the first barrier insulation film;
a second barrier conductive pattern electrically connected to an upper surface of the bit line;
a second barrier insulation film that surrounds side surfaces of the second barrier conductive pattern; and
a second memory cell that electrically connects the second barrier conductive pattern and the second word line, on an upper surface of the second barrier conductive pattern and an upper surface of the second barrier insulation film,
wherein each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching (OTS) properties and a phase change pattern in which resistance changes depending on a phase change.
20. The semiconductor memory device of claim 19 ,
wherein each of the first memory cell and the second memory cell further includes:
a lower electrode pattern between the first barrier conductive pattern and the selection pattern;
a central electrode pattern between the selection pattern and the phase change pattern; and
an upper electrode pattern on the central electrode pattern, and
wherein the phase change pattern is between the upper electrode pattern and the central electrode pattern.