Method for accelerating deep sleep startup speed in IoT
A method for accelerating sleep startup speed is provided. The method may include determining that a system-on-chip (SoC) is under a sleep mode; determining that a wake-up condition is met; calculating a second authentication key based on data stored in a flash memory of the SoC using a cryptographic algorithm; comparing the second authentication key with a first authentication key, wherein the first authentication key is associated with a secure boot of the SoC and obtained from an Always On (AON) memory of the SoC; and in response to a comparison result that the first authentication key is the same as the second authentication key, waking the SoC up from the sleep mode.
1. A method comprising:
determining that a system-on-chip (SoC) is under a sleep mode;
determining that a wake-up condition is met;
calculating a second authentication key based on data stored in a flash memory of the SoC using a cryptographic algorithm;
comparing the second authentication key with a first authentication key, wherein the first authentication key is associated with a secure boot of the SoC and obtained from an Always On (AON) memory of the SoC; and
in response to a comparison result that the first authentication key is the same as the second authentication key, waking the SoC up from the sleep mode.
2. The method of claim 1 , wherein the first authentication key is written on the AON memory before the SoC enters the sleep mode.
3. The method of claim 1 , further comprising:
in response to a comparison result that the first authentication key is different from the second authentication key, holding the SoC in the sleep mode.
4. The method of claim 3 , wherein in response to the comparison result that the first authentication key is different from the second authentication key, the method further comprises:
generating a notification that the SoC is attacked during the sleep mode.
5. The method of claim 1 , wherein the second authentication key comprises:
a signature key calculated based on signature data read from the flash memory.
6. The method of claim 1 , wherein the second authentication key comprises:
an image key calculated based on a code image read from the flash memory.
7. The method of claim 1 , wherein the second authentication key does not include a public key.
8. The method of claim 1 , wherein the comparing the first authentication key with the second authentication key comprises:
comparing a part of the first authentication key with a corresponding part of the second authentication key.
9. The method of claim 1 , wherein the comparing the first authentication key with second authentication key comprises:
comparing first 32 bits of the first authentication key with first 32 bits of the second authentication key.
10. The method of claim 1 , wherein the first authentication key is read from a one-time programmable (OTP) memory of the SoC during the secure boot of the SoC.
11. The method of claim 1 , wherein the wake-up condition comprises:
receiving a wake-up instruction signal from an external device;
pasting a pre-determined time duration under the sleep mode; or
receiving a wake-up triggering signal from an internal component of the SoC.
12. A system-on-chip (SoC) comprising:
a processor configured to:
determine that the SoC is under a sleep mode;
determine that a wake-up condition is met;
calculate a second authentication key based on data stored in a flash memory of the SoC using a cryptographic algorithm;
compare the second authentication key with a first authentication key, wherein the first authentication key is associated with a secure boot of the SoC and obtained from an Always On (AON) memory of the SoC; and
in response to a comparison result that the first authentication key is the same as the second authentication key, wake the SoC up from the sleep mode.
13. The SoC of claim 12 , wherein the first authentication key is written on the AON memory before the SoC enters the sleep mode.
14. The SoC of claim 12 , wherein the processor is further configured to:
in response to a comparison result that the first authentication key is different from the second authentication key, hold the SoC in the sleep mode and generate a notification that the SoC is attacked during the sleep mode.
15. The SoC of claim 12 , wherein the second authentication key comprises:
a signature key calculated based on signature data read from the flash memory.
16. The SoC of claim 12 , wherein the second authentication key comprises:
an image key calculated based on a code image read from the flash memory.
17. The SoC of claim 12 , wherein the comparing the first authentication key with the second authentication key comprises:
comparing a part of the first authentication key with a corresponding part of the second authentication key.
18. The SoC of claim 12 , wherein the first authentication key is read from a one-time programmable (OTP) memory of the SoC during the secure boot of the SoC.
19. The SoC of claim 12 , wherein the wake-up condition comprises:
receiving a wake-up instruction signal from an external device;
pasting a pre-determined time duration under the sleep mode; or
receiving a wake-up triggering signal from an internal component of the SoC.
20. A non-transitory computer-readable storage medium, the computer-readable storage medium including instructions that when executed by a computer, cause the computer to:
determine that a system-on-chip (SoC) is under a sleep mode;
determine that a wake-up condition is met;
calculate a second authentication key based on data stored in a flash memory of the SoC using a cryptographic algorithm;
compare the second authentication key with a first authentication key, wherein the first authentication key is associated with a secure boot of the SoC and obtained from an Always On (AON) memory of the SoC; and
in response to a comparison result that the first authentication key is the same as the second authentication key, wake the SoC up from the sleep mode.