Automatic clock rate synchronization for 1-wire radio frequency front-end interface
A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.
1. A clock generation circuit, comprising:
a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus;
a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal;
a comparator configured to:
drive a decision signal to a first signaling state when the output of the counter matches the latched output; and
drive the decision signal to a second signaling state when the output of the counter does not match the latched output; and
a flipflop having an output that changes signaling state in response to an edge in the decision signal,
wherein the counter is reset when the decision signal is driven to the first signaling state.
2. The clock generation circuit of claim 1 , wherein the latched output represents the transitions counted in the locally generated clock signal during a portion of the synchronization pattern.
3. The clock generation circuit of claim 2 , wherein the portion of the synchronization pattern includes two transitions in signaling state of the data signal.
4. The clock generation circuit of claim 2 , wherein the portion of the synchronization pattern corresponds to one or more bit transmission intervals.
5. The clock generation circuit of claim 2 , wherein the portion of the synchronization pattern corresponds to one and a half bit transmission intervals.
6. The clock generation circuit of claim 1 , further comprising gating logic configured to select bits of the output of the counter to be captured by the latch.
7. The clock generation circuit of claim 1 , further comprising a controller that is configured to:
enable the latch and the counter when the synchronization pattern is being received in the data signal; and
enable the counter and the flipflop after the synchronization pattern has been terminated and while transitions are detected in the data signal.
8. The clock generation circuit of claim 7 , wherein the controller is further configured to:
disable the flipflop when the synchronization pattern is being received in the data signal; and
disable the latch after the synchronization pattern has been terminated,
wherein the output of the flipflop provides a receive clock signal that has a frequency matched to a data rate associated with the data signal.
9. The clock generation circuit of claim 7 , wherein the controller is further configured to reset the counter when a transition is detected at a center of a bit transmission interval after the synchronization pattern has been terminated.
10. The clock generation circuit of claim 1 , wherein the data signal is encoded using Manchester encoding.
11. An apparatus comprising:
means for counting transitions in a locally generated clock signal, including a counter configured to count the transitions when a data signal is received from a 1-wire serial bus;
means for capturing an output of the counter, including a latch configured to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal;
means for comparing the output of the counter and the latched output, including a comparator configured to:
drive a decision signal to a first signaling state when the output of the counter matches the latched output; and
drive the decision signal to a second signaling state when the output of the counter does not match the latched output; and
a flipflop clocked by the decision signal and having an output that changes signaling state in response to an edge in the decision signal,
wherein the counter is reset when the decision signal is driven to the first signaling state.
12. The apparatus of claim 11 , wherein the latched output represents the transitions counted in the locally generated clock signal during a portion of the synchronization pattern.
13. The apparatus of claim 12 , wherein the portion of the synchronization pattern includes two transitions in signaling state of the data signal.
14. The apparatus of claim 12 , wherein the portion of the synchronization pattern corresponds to one or more bit transmission intervals.
15. The apparatus of claim 12 , wherein the portion of the synchronization pattern corresponds to one and a half bit transmission intervals.
16. The apparatus of claim 11 , wherein the means for capturing the output of the counter comprises gating logic configured to select bits of the output of the counter to be captured by the latch.
17. The apparatus of claim 11 , further comprising a controller configured to:
enable the latch and the counter when the synchronization pattern is being received in the data signal; and
enable the counter and the flipflop after the synchronization pattern has been terminated and while transitions are detected in the data signal.
18. The apparatus of claim 17 , wherein the controller is further configured to:
disable the flipflop when the synchronization pattern is being received in the data signal; and
disable the latch after the synchronization pattern has been terminated.
19. The apparatus of claim 17 , wherein the controller is further configured to reset the counter when a transition is detected at a center of a bit transmission interval after the synchronization pattern has been terminated.
20. The apparatus of claim 11 , wherein the data signal is encoded using Manchester encoding.
21. A method for generating a rate matched clock signal, comprising:
configuring a counter to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus;
configuring a latch to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal; and
configuring a comparator to:
drive a decision signal to a first signaling state when the output of the counter matches the latched output; and
drive the decision signal to a second signaling state when the output of the counter does not match the latched output,
wherein the decision signal is configured to clock a flipflop that has an output that changes signaling state in response to an edge in the decision signal, and
wherein the counter is reset when the decision signal is driven to the first signaling state.
22. The method of claim 21 , wherein the latched output represents the transitions counted in the locally generated clock signal during a portion of the synchronization pattern.
23. The method of claim 22 , wherein the portion of the synchronization pattern includes two transitions in signaling state of the data signal.
24. The method of claim 22 , wherein the portion of the synchronization pattern corresponds to one or more bit transmission intervals.
25. The method of claim 22 , wherein the portion of the synchronization pattern corresponds to one and a half bit transmission intervals.
26. The method of claim 21 , further comprising configuring gating logic to select bits of the output of the counter to be captured by the latch.
27. The method of claim 21 , wherein a controller is configured to:
enable the latch and the counter when the synchronization pattern is being received in the data signal; and
enable the counter and the flipflop after the synchronization pattern has been terminated and while transitions are detected in the data signal.
28. The method of claim 27 , wherein the controller is further configured to:
disable the flipflop when the synchronization pattern is being received in the data signal; and
disable the latch after the synchronization pattern has been terminated.
29. The method of claim 27 , wherein the controller is further configured to reset the counter when a transition is detected at a center of a bit transmission interval after the synchronization pattern has been terminated.
30. The method of claim 21 , wherein the data signal is encoded using Manchester encoding.