Granted Patent B2

US 12,284,341 · App. 18/062,455 · Granted Apr 22, 2025

Inventors: Ryuichi Kanoh (Osaka, JP); Takahiro Nishi (Nara, JP); Tadamasa Toma (Osaka, JP)

Assignee: Panasonic Intellectual Property Corporation of America

H04N19/117H04N19/136H04N19/159H04N19/176H04N19/182H04N19/61H04N19/82

Abstract

Claims (20)

1. A decoder comprising:

a memory; and

processing circuitry, which is coupled to the memory and which, in operation, changes values of pixels in a first block and a second block to filter a boundary between the first block and the second block, using clipping such that change amounts of the respective values are within respective clip widths, the pixels in the first block and the second block being arranged along a straight line across the boundary;

wherein the clip widths for the pixels in the first block and the second block are selected to be asymmetrical based on the block sizes;

wherein the pixels in the first block include a first pixel located at a first position, and the pixels in the second block include a second pixel located at a second position corresponding to the first position with respect to the boundary;

wherein the clip widths include a first clip width and a second clip width corresponding to the first pixel and the second pixel, respectively;

wherein the first clip width is larger than the second clip width when the first block is larger than the second block;

wherein the pixels in the first block include a first additional pixel located at a first additional position and the pixels in the second block include a second additional pixel located at a second additional position which corresponds to the first additional position with respect to the boundary;

wherein the clip widths include a first additional clip width and a second additional clip width corresponding to the first additional pixel and the second additional pixel, respectively; and

wherein the first additional clip width is same as the second additional clip width.

2. An encoder comprising:

a memory; and

processing circuitry, which is coupled to the memory and which, in operation, changes values of pixels in a first block and a second block to filter a boundary between the first block and the second block, using clipping such that change amounts of the respective values are within respective clip widths, the pixels in the first block and the second block being arranged along a straight line across the boundary;

wherein the clip widths for the pixels in the first block and the second block are selected to be asymmetrical based on the block sizes;

wherein the pixels in the first block include a first pixel located at a first position, and the pixels in the second block include a second pixel located at a second position corresponding to the first position with respect to the boundary;

wherein the clip widths include a first clip width and a second clip width corresponding to the first pixel and the second pixel, respectively;

wherein the first clip width is larger than the second clip width when the first block is larger than the second block;

wherein the pixels in the first block include a first additional pixel located at a first additional position and the pixels in the second block include a second additional pixel located at a second additional position which corresponds to the first additional position with respect to the boundary;

wherein the clip widths include a first additional clip width and a second additional clip width corresponding to the first additional pixel and the second additional pixel, respectively; and

wherein the first additional clip width is same as the second additional clip width.

Continuity (5)

References Cited (57)