Resetting system settings memories
A method for resetting a system settings memory of processing circuitry of a computing system includes determining that a reset of the system settings memory is needed. At a controller coupled with a relay-based hardware circuit positioned between the system settings memory and a battery that backs the system setting memory, the method includes initiating clearing of the system settings memory of the processing circuitry of the computing system. Based on determining that a predetermined time period has passed from initiating the clearing of the system settings memory of the processing circuitry of the computing system, the method includes proceeding with a boot sequence for the computing system.
1. A system comprising:
a controller;
processing circuitry comprising a processing resource and a system settings memory;
a battery to back up the system settings memory; and
a default closed relay-based hardware circuit coupled between the battery and the system settings memory;
wherein the controller is coupled with the relay-based hardware circuit,
wherein the controller is configured to initiate clearing of the system settings memory of the processing circuitry by changing a state of the relay-based hardware circuit,
wherein the controller is configured to determine that a predetermined time period has passed since initiation of clearing of the system settings memory of the processing circuitry, and
wherein the controller is configured to cause, based on determining, by the controller, that the predetermined time period has passed since initiation of clearing of the system settings memory of the processing circuitry, a boot sequence for the system to proceed.
2. The system of claim 1 , wherein the controller is configured to initiate clearing of the system settings memory of the processing circuitry by controlling the state of the relay-based hardware circuit by toggling a switch of the relay-based hardware circuit from a closed state to an open state for a predetermined time period, wherein in the closed state the battery is configured to supply power to the system settings memory and in the open state the battery is configured not to supply power to the system settings memory.
3. The system of claim 2 , wherein the controller is configured to cause a boot sequence for the system to proceed by toggling the switch of the relay-based hardware circuit from the open state to the closed state based on determining that the predetermined time period has passed.
4. The system of claim 2 , wherein the predetermined time period is greater than or equal to 20 ms.
5. The system of claim 1 , wherein the controller is configured to initiate clearing of the system settings memory of the processing circuitry by controlling the state of the relay-based hardware circuit in a state in which power is not supplied by a power supply subsystem to the system settings memory of the processing circuitry.
6. The system of claim 1 , wherein the system settings memory comprises a complementary metal oxide semiconductor (CMOS).
7. A method for resetting a system settings memory of processing circuitry of a computing device, the method comprising:
determining, by a controller, to reset the system settings memory;
initiating, by the controller coupled with a default closed relay-based hardware circuit coupled between the system settings memory and a battery that backs the system settings memory, clearing of the system settings memory of the processing circuitry of the computing device by changing a state of the relay-based hardware circuit;
determining, by the controller, that a predetermined time period has passed since initiation of clearing of the system settings memory of the processing circuitry of the computing device; and
causing, by the controller, based on determining, by the controller, that the predetermined time period has passed since initiating clearing of the system settings memory of the processing circuitry of the computing device, a boot sequence for the computing device to proceed.
8. The method of claim 7 , wherein determining to reset the system settings memory comprises receiving, at the controller, a request to reset the system settings memory of the processing circuitry of the computing device.
9. The method of claim 7 , wherein determining to reset the system settings memory comprises determining that an error occurred during execution of the boot sequence for the computing device.
10. The method of claim 7 , wherein determining to reset the system settings memory comprises determining that the computing device has not ever previously been booted.
11. The method of claim 7 , wherein initiating clearing of the system settings memory of the processing circuitry of the computing device comprises toggling a switch of the relay-based hardware circuit from a closed state to an open state for the predetermined time period, wherein in the closed state the battery is configured to supply power to the system settings memory and in the open state the battery is configured not to supply power to the system settings memory.
12. The method of claim 11 , wherein the method further comprises toggling the switch of the relay-based hardware circuit from the open state to the closed state based on determining that the predetermined time period has passed.
13. The method of claim 7 , wherein clearing of the system settings memory of the processing circuitry of the computing device by controlling the state of the relay-based hardware circuit is initiated in a state in which power is not supplied by a power supply subsystem to the system settings memory of the processing circuitry.
14. The method of claim 7 , wherein the system settings memory comprises a complementary metal oxide semiconductor (CMOS).
15. The method of claim 7 , wherein the predetermined time period is greater than or equal to 20 ms.
16. A non-transitory computer-readable storage medium having stored thereon, a set of computer-executable instructions for causing one or more processing resources of a controller of a computing system to:
receive power at the controller;
initiate, by the controller, clearing of a system settings memory of the computing system by changing a state of a default closed relay-based hardware circuit positioned in a power supply path between the system settings memory and a battery that backs the system settings memory;
determine, by the controller, that a predetermined time period has passed since initiation of clearing of the system settings memory of the computing system; and
cause, by the controller, based on determining, by the controller, that the predetermined time period has passed, a boot sequence for the computing system to proceed.
17. The non-transitory computer-readable storage medium of claim 16 , wherein the set of computer-executable instructions cause the one or more processing resources to initiate clearing of the system settings memory of the computing system utilizing the relay-based hardware circuit by toggling a switch of the relay-based hardware circuit from a closed state to an open state for the predetermined time period, wherein in the closed state the battery is configured to supply power to the system settings memory and in the open state the battery is configured not to supply power to the system settings memory.
18. The non-transitory computer-readable storage medium of claim 17 , wherein the set of computer-executable instructions cause the one or more processing resources to toggle the switch of the relay-based hardware circuit from the open state to the closed state based on determining that the predetermined time period has passed.
19. The non-transitory computer-readable storage medium of claim 16 , wherein initiating clearing of the system settings memory of the computing system causes a reset of one or more system settings to a default system setting.
20. The non-transitory computer-readable storage medium of claim 16 , wherein the set of computer-executable instructions cause the one or more processing resources to initiate clearing of the system settings memory of the computing system based on determining, from an internal non-volatile memory of the controller, that the controller has not previously received power.