Operation fusion for instructions bridging execution unit types
Techniques are disclosed that relate to fusing operations for execution of certain instructions. A processor may include a first execution circuit, of a first type, coupled to a first register file, a second execution circuit, of a second type, coupled to a second register file and a load/store circuit coupled to the first and second register files. The load/store circuit includes an issue port configured to receive an instruction operation for execution, a memory execution circuit configured to execute memory access operations, and a register transfer execution circuit. The register transfer execution circuit is configured to execute instruction operations specifying data transfer from the first register file to the second register file and an operation to be performed using the data, and the load/store circuit is configured to direct a given instruction operation from the issue port to one of the memory execution circuit or the register transfer execution circuit.
1. A processor, comprising:
a first execution circuit of a first type;
a second execution circuit of a second type different from the first type;
a first register file coupled to the first execution circuit;
a second register file coupled to the second execution circuit; and
a load/store circuit coupled to the first register file and the second register file, the load/store circuit comprising:
an issue port configured to receive an instruction operation for execution;
a memory execution circuit configured to execute memory access instruction operations; and
a register transfer execution circuit configured to execute an instruction operation specifying a transfer of data from the first register file to the second register file and further specifying an additional operation to be performed using the data; and
wherein the load/store circuit is configured to direct a given instruction operation from the issue port to one of the memory execution circuit or the register transfer execution circuit.
2. The processor of claim 1 , wherein the first execution circuit is an integer execution circuit and the second execution circuit is a floating-point execution circuit.
3. The processor of claim 1 , wherein the first execution circuit is a scalar execution circuit and the second execution circuit is a vector execution circuit.
4. The processor of claim 1 , wherein the first register file comprises a general-purpose register file.
5. The processor of claim 1 , wherein:
the additional operation is an integer-to-floating-point conversion operation; and
the register transfer execution circuit includes an integer-to-floating-point conversion circuit.
6. The processor of claim 5 , wherein the second execution circuit includes an additional integer-to-floating point conversion circuit.
7. The processor of claim 1 , wherein:
the additional operation is a duplication operation; and
the register transfer execution circuit includes a duplication circuit configured to read a value from the first register file and copy the value to one or more vector elements stored in the second register file.
8. The processor of claim 1 , further comprising a decoder circuit coupled to the load/store circuit, wherein the decoder circuit is configured to:
receive a fetched transfer instruction involving transfer of data from the first register file to the second register file; and
decode the fetched transfer instruction into an instruction operation for execution by the register transfer execution circuit.
9. The processor of claim 1 , wherein the first register file is not directly accessible by the second execution circuit and the second register file is not directly accessible by the first execution circuit.
10. The processor of claim 1 , wherein the first register file is configured to store values of the first type and the second register file is configured to store values of the second type.
11. The processor of claim 1 , wherein the issue port comprises a reservation station.
12. The processor of claim 1 , further comprising a dispatch circuit configured to issue to the load/store circuit the instruction operation specifying a transfer of data from the first register file to the second register file and further specifying an additional operation to be performed using the data.
13. The processor of claim 12 , wherein the dispatch circuit is configured to issue the instruction operation to the issue port of the load/store circuit.
14. A method, comprising:
detecting, by a processor, an instruction specifying a transfer of data between first and second register files of the processor and further specifying an additional operation to be performed using the data, wherein the first and second register files are coupled to respective first and second execution circuits of the processor, and wherein the first and second execution circuits are of different types;
decoding, by the processor, the instruction into an instruction operation for execution by a register transfer execution circuit in a load/store circuit of the processor;
receiving, by the processor, the instruction operation at the load/store circuit; and
executing, by the processor and using the register transfer execution circuit, the instruction operation.
15. The method of claim 14 , wherein:
specifying the additional operation includes specifying conversion of an integer value from the first register file to a floating-point value; and
the register transfer execution circuit includes an integer-to-floating-point conversion circuit.
16. The method of claim 14 , wherein
specifying the additional operation includes specifying reading of a scalar value from the first register file and copying of the scalar value to one or more vector elements stored in the second register file.
17. The method of claim 14 , further comprising dispatching, by the processor, the instruction operation to an issue port of the load/store circuit.
18. A non-transitory computer readable medium having stored thereon design information that specifies, in a format recognized by a fabrication system that is configured to use the design information, a circuit design for a processor, the processor comprising:
a first execution circuit of a first type;
a second execution circuit of a second type different from the first type;
a first register file coupled to the first execution circuit;
a second register file coupled to the second execution circuit; and
a load/store circuit coupled to the first register file and the second register file, the load/store circuit comprising:
an issue port configured to receive an instruction operation for execution;
a memory execution circuit configured to execute memory access instruction operations; and
a register transfer execution circuit configured to execute an instruction operation specifying a transfer of data from the first register file to the second register file and further specifying an additional operation to be performed using the data; and
wherein the load/store circuit is configured to direct a given instruction operation from the issue port to one of the memory execution circuit or the register transfer execution circuit.
19. The computer readable medium of claim 18 , wherein:
the first execution circuit is an integer execution circuit;
the second execution circuit is a floating-point execution circuit;
the additional operation is an integer-to-floating point conversion operation; and
the register transfer execution circuit includes an integer-to-floating-point conversion circuit.
20. The computer readable medium of claim 18 , wherein:
the first execution circuit is a scalar execution circuit;
the second execution circuit is a vector execution circuit;
the additional operation is a duplication operation; and
the register transfer execution circuit includes a duplication circuit configured to read a value from the first register file and copy the value to one or more vector elements stored in the second register file.