IP Library › Granted Patent US 12,288,130
Granted Patent B2
US 12,288,130 · App. 18/586,154 · Granted Apr 29, 2025

Methods and apparatus for performing phase operations

Inventor: Craig Gidney (Goleta, CA)
Assignee: Google LLC
G06N10/20G06N10/40H03K19/20
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Quick Facts
Patent No.
US 12,288,130
App. No.
18/586,154
Granted
Apr 29, 2025
Kind
B2
Abstract

Methods, systems, and apparatus for performing phase operations. In one aspect, a method for performing a same phase operation on a first and second qubit using a third qubit prepared in a phased plus state includes: performing a first NOT operation on the third qubit; computing a controlled adder operation on the first, second and third qubit, comprising encoding the result of the controlled adder operation in a fourth qubit; performing a square of the phase operation on the fourth qubit; uncomputing the controlled adder operation on the first, second and third qubit; performing a CNOT operation between the first qubit and the third qubit, wherein the first qubit acts as the control; performing a CNOT operation between the second qubit and the third qubit, wherein the second qubit acts as the control; and performing a second NOT operation on the third qubit.

Claims (101)

1. A method, performed by a quantum computing device, for applying a target phase to a first qubit and a second qubit by performing a phase operation on a first and second qubit using a third qubit prepared in a phased plus state, wherein the phased plus state comprises a plus state that has been phased by an angle equivalent to the target phase, comprising:

performing a first NOT operation on the third qubit;

performing a first multi target CNOT gate on the first, second and third qubits, wherein the first and second qubits comprise target qubits and the third qubit acts as a control;

performing a first CNOT gate on the third qubit, wherein the first and second qubits act as controls;

performing a square phase operation on the third qubit,

performing a second CNOT operation on the third qubit, wherein the first and second qubits act as controls;

performing a second multi target CNOT gate on the first, second and third qubits, wherein the first and second qubits comprise target qubits and the third qubit acts as a control;

performing a third CNOT gate on the third qubit, wherein the first qubit acts as a control;

performing a fourth CNOT gate on the third qubit, wherein the second qubit acts as the control; and

performing a second NOT operation on the third qubit.

2. The method of claim 1 , wherein performing the second NOT operation on the third qubit returns the third qubit to the phased plus state.

3. The method of claim 1 , wherein the first and second qubits are initially prepared in arbitrary initial states.

4. The method of claim 1 , wherein:

the first qubit is prepared in an arbitrary initial state, the second qubit is prepared in a plus state, and the third qubit is prepared in a phased plus state; and

after performing the second NOT operation on the third qubit, the second qubit is in a phased plus state, the third qubit is in a phased plus state, and the phase operation has been performed on the first qubit.

5. The method of claim 4 , further comprising providing the second qubit in the phased plus state for use in a gate teleportation operation.

6. The method of claim 5 , wherein the gate teleportation operation comprises one of:

performing a second phase operation on a fifth and sixth qubits;

preparing a sixth qubit in a same state as a seventh qubit when performing a phase operation on a fifth qubit; or

performing the phase operation on a fifth qubit.

7. The method of claim 6 , wherein performing the phase operation on a fifth qubit comprises:

applying a CNOT operation between the second qubit prepared in the phased plus state and the fifth qubit prepared in an arbitrary state, wherein the fifth qubit acts as the control;

measuring the second qubit; and

applying a squared phase operation to the fifth qubit if a generated measurement result from measuring the second qubit indicates that the second qubit is ON.

8. The method of claim 4 , wherein performing the square phase operation on the third qubit comprises preparing a sixth qubit in a same state as a seventh qubit when performing the square phase operation on a fifth qubit.

9. The method of claim 8 , further comprising iteratively performing squares of the phase operation.

10. The method of claim 1 , wherein the phase operation comprises a single qubit operation of the form

Z

θ

=

(

1

0

0

e

i

⁢

πθ

)

where θ specifies the phase operation, and wherein the square of the phase operation is given by Z 2θ .

11. The method of claim 1 , wherein the phased plus state comprises the phase operation applied to a plus state ├|+ =(|0 +|1 )/√2, and/or wherein the phase operation comprises a

T

=

Z

π

8

operation.

12. The method of claim 1 , further comprising, for a system requiring N phase operations to be performed on multiple respective qubits:

grouping qubits that require a phase operation into O(sqrt(N)) groups of size O(sqrt(N));

preparing a full-total qubit register of size O(log(N));

for each group:

computing a Hamming weight of the qubits in the group;

adding a computed group-total into the full-total register;

uncompute the Hamming weight of the qubits in the group;

performing phase operations on the full-total register;

for each group:

computing a Hamming weight of the qubits in the group;

subtracting a computed group-total out of the full-total register; and

uncomputing the Hamming weight of the qubits in the group,

optionally further comprising clearing and discarding the full-total register.

13. An apparatus ( 100 ) comprising quantum hardware ( 102 ) in data communication with one or more classical processors ( 104 ), wherein the quantum hardware is configured to perform operations for applying a target phase to a first qubit and a second qubit by performing a phase operation on a first and second qubit using a third qubit prepared in a phased plus state, wherein the phased plus state comprises a plus state that has been phased by an angle equivalent to the target phase, the operations comprising:

performing a first NOT operation on the third qubit;

performing a first multi target CNOT gate on the first, second and third qubits, wherein the first and second qubits comprise target qubits and the third qubit acts as a control;

performing a first CNOT gate on the third qubit, wherein the first and second qubits act as controls;

performing a square phase operation on the third qubit,

performing a second CNOT operation on the third qubit, wherein the first and second qubits act as controls;

performing a second multi target CNOT gate on the first, second and third qubits, wherein the first and second qubits comprise target qubits and the third qubit acts as a control;

performing a third CNOT gate on the third qubit, wherein the first qubit acts as a control;

performing a fourth CNOT gate on the third qubit, wherein the second qubit acts as the control; and

performing a second NOT operation on the third qubit.

14. The apparatus of claim 13 , wherein the quantum hardware comprises:

a register of qubits;

a plurality of control lines coupled to the register of qubits; and

a plurality of control circuits coupled to the plurality of control lines.

15. The apparatus of claim 13 , wherein:

the first qubit is prepared in an arbitrary initial state, the second qubit is prepared in a plus state, and the third qubit is prepared in a phased plus state; and

after performing the second NOT operation on the third qubit, the second qubit is in a phased plus state, the third qubit is in a phased plus state, and the phase operation has been performed on the first qubit.

16. The apparatus of claim 15 , further comprising providing the second qubit in the phased plus state for use in a gate teleportation operation.

17. The apparatus of claim 13 , wherein performing the second NOT operation on the third qubit returns the third qubit to the phased plus state.

18. The apparatus of claim 13 , wherein the first and second qubits are initially prepared in arbitrary initial states.

19. The apparatus of claim 13 , wherein the phase operation comprises a single qubit operation of the form

Z

θ

=

(

1

0

0

e

i

⁢

πθ

)

where θ specifies the phase operation, and wherein the square of the phase operation is given by Z 2θ .

20. The apparatus of claim 13 , wherein the phased plus state comprises the phase operation applied to a plus state ├|+ =(|0 +|1 )/√2, and/or wherein the phase operation comprises a

T

=

Z

π

8

operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2024
From: GIDNEY, CRAIG
To: GOOGLE LLC
Reel/Frame 066833/0053 →
Continuity (4)
Continuation 18181419 · Mar 9, 2023
Continuation 16753699
Provisional Application 62658993 · Apr 17, 2018
Related Publication 20240232673A1 · Jul 11, 2024
References Cited (31)
US 20030164490A1 · Blais · 2003 [cited by applicant]
US 20080310000A1 · Beausoleil et al. · 2008 [cited by applicant]
US 20140118024A1 · Eastin · 2014 [cited by applicant]
US 20160142057A1 · Melton et al. · 2016 [cited by applicant]
US 20170351967A1 · Babbush et al. · 2017 [cited by applicant]
US 20180053112A1 · Bravyi · 2018 [cited by examiner]
US 20200311594A1 · Gidney · 2020 [cited by examiner]
US 20220067567A1 · O'Brien · 2022 [cited by examiner]
CN 101118608 · 2008 [cited by applicant]
JP 2016500886 · 2016 [cited by applicant]
WO WO2019050555 · 2019 [cited by applicant]
Barends et al. “Superconducting quantum circuits at the surface code threshold for fault tolerance,” Nature, Apr. 24, 2014, 15 pages. [cited by applicant]
Bravyi et al., “Universal Quantum Computation with ideal Clifford gates and noisy ancillas” CoRR, submitted on Dec. 16, 2004, arXiv:quant-ph/0403025v2, 14 pages. [cited by applicant]
Garcia-Escartin et al., “Equivalent Quantum Circuits,” CoRR, submitted on Oct. 13, 2011, arXiv:1110.2998v1, 12 pages. [cited by applicant]
Gidney, “Halving the cost of quantum addition,” CoRR, submitted on Jan. 19, 2018, arXiv 1709.06648v2, 5 pages. [cited by applicant]
Gidney, “Proxy Phasing and Computed Phasing,” Algorithmic Assertions, 2017, 8 pages. [cited by applicant]
International Preliminary Report on Patentability in International Appln. No. PCT/US2019/027640, mailed on Oct. 29, 2020, 11 pages. [cited by applicant]
International Search Report and Written Opinion issued in International Appln. No. PCT/US2019/027640, mailed on Jul. 31, 2019, 17 pages. [cited by applicant]
Kivlichan et al. “Improved Fault-Tolerant Quantum Simulation of Condensed-Phase Correlated Electrons via Trotterization,” arXiv 1902.10673v1, Feb. 27, 2019, 35 pages. [cited by applicant]
Notice of Allowance in Australian Appln. No. 2022201377, mailed on Sep. 21, 2023, 3 pages. [cited by applicant]
Office Action in Australian Appln. No. 2022201377, mailed on Feb. 23, 2023, 3 pages. [cited by applicant]
Office Action in Australian Appln. No. 2019255217, mailed on Jan. 4, 2021, 3 pages. [cited by applicant]
Office Action in Australian Appln. No. 2019255217, mailed on Oct. 15, 2020, 4 pages. [cited by applicant]
Office Action in Canadian Appln. No. 3,080,180, mailed on Jun. 30, 2023, 5 pages. [cited by applicant]
Office Action in Canadian Appln. No. 3,080,180, mailed on Jun. 7, 2021, 3 pages. [cited by applicant]
Office Action in Chinese Appln. No. 201980005351.2, mailed on Apr. 8, 2023, 12 pages (with English translation). [cited by applicant]
Office Action in European Appln. No. 19721473.7, mailed on Oct. 13, 2021, 13 pages. [cited by applicant]
Office Action in European Appln. No. 19721473.7, mailed on Apr. 17, 2024, 12 pages. [cited by applicant]
Office Action in Japanese Appln. No. 2021-130663, mailed on Sep. 5, 2022, 5 pages (with English Translation). [cited by applicant]
Oliveira et al., “A probabilistic CNOT gate for coherent state qubits,”, Physics Letters A, Nov. 22, 2013, 377(39):2821-2825. [cited by applicant]
Paetznick, “Resource optimization for fault-tolerant quantum computing,” Thesis for PhD in Computer Science at University of Waterloo, Dec. 13, 2013, 116 pages. [cited by applicant]