IP Library › Granted Patent US 12,288,797
Granted Patent B2
US 12,288,797 · App. 17/710,249 · Granted Apr 29, 2025

Image sensor

Inventors: Junghyun Kim (Suwon-si, KR); Bumsuk Kim (Hwaseong-si, KR); Jonghoon Park (Seoul, KR); Hyungeun Yoo (Suwon-si, KR); Yun Ki Lee (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L27/1463H01L27/14621H01L27/14627H01L27/1464H01L27/14645H01L27/14689H04N25/702
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Quick Facts
Patent No.
US 12,288,797
App. No.
17/710,249
Granted
Apr 29, 2025
Kind
B2
Abstract

An image sensor includes a substrate including pixel regions and having a first surface, a second surface opposite the first surface, and a first trench recessed from the first surface, a shallow device isolation pattern provided in the first trench, and a deep device isolation pattern between the pixel regions and provided in the substrate. The deep device isolation pattern includes a semiconductor pattern penetrating at least a portion of the substrate, and an isolation pattern provided between the substrate and the semiconductor pattern. The isolation pattern includes a first isolation pattern adjacent to the second surface, and a second isolation pattern adjacent to the first surface. A first interface at which the first isolation pattern contacts the second isolation pattern is spaced apart from the shallow device isolation pattern. The first isolation pattern includes a different material from that of the second isolation pattern.

Claims (57)

1. An image sensor comprising:

a substrate comprising a plurality of pixel regions, the substrate having a first surface, a second surface opposite the first surface, and a first trench recessed from the first surface;

a shallow device isolation pattern provided in the first trench; and

a deep device isolation pattern provided in the substrate between pixel regions of the plurality of pixel regions,

wherein the deep device isolation pattern comprises a semiconductor pattern penetrating at least a portion of the substrate, and an isolation pattern provided between the substrate and the semiconductor pattern,

wherein the isolation pattern comprises a first isolation pattern adjacent to the second surface of the substrate, and a second isolation pattern adjacent to the first surface of the substrate,

wherein a first interface at which the first isolation pattern contacts the second isolation pattern is spaced apart from the shallow device isolation pattern, and

wherein the first isolation pattern comprises a first material, and the second isolation pattern comprises a second material that is different from the first material.

2. The image sensor of claim 1 , wherein the second isolation pattern comprises a lower portion disposed under the shallow device isolation pattern, and an upper portion penetrating the shallow device isolation pattern,

wherein a first side surface of the lower portion of the second isolation pattern is adjacent to the substrate, and a second side surface of the lower portion of the second isolation pattern is adjacent to the semiconductor pattern,

wherein a first side surface of the first isolation pattern is adjacent to the substrate, and a second side surface of the first isolation pattern is adjacent to the semiconductor pattern,

wherein the first side surface of the lower portion of the second isolation pattern is aligned with the first side surface of the first isolation pattern, and

wherein the second side surface of the lower portion of the second isolation pattern is aligned with the second side surface of the first isolation pattern.

3. The image sensor of claim 1 , wherein the deep device isolation pattern further comprises an insulating pattern disposed on the semiconductor pattern and penetrating the shallow device isolation pattern, and

wherein the isolation pattern extends between the shallow device isolation pattern and the insulating pattern.

4. The image sensor of claim 1 , wherein a bottom surface of the deep device isolation pattern is substantially coplanar with the second surface of the substrate.

5. The image sensor of claim 1 , wherein a refractive index of the first isolation pattern is in a range from 1 to 2.

6. The image sensor of claim 1 , wherein a dielectric constant of the second isolation pattern ranges is in a range from 4 to 25.

7. The image sensor of claim 1 , wherein the isolation pattern further comprises a third isolation pattern provided on the second isolation pattern, and

wherein the third isolation pattern comprises a third material that is different from the second material of the second isolation pattern.

8. The image sensor of claim 7 , wherein a second interface at which the second isolation pattern contacts the third isolation pattern is spaced apart from the shallow device isolation pattern.

9. The image sensor of claim 7 , wherein the third isolation pattern comprises a lower portion disposed under the shallow device isolation pattern and an upper portion penetrating the shallow device isolation pattern,

wherein a first side surface of the lower portion of the third isolation pattern is adjacent to the substrate, and a second side surface of the lower portion of the third isolation pattern is adjacent to the semiconductor pattern,

wherein a first side surface of the second isolation pattern is adjacent to the substrate, and a second side surface of the second isolation pattern is adjacent to the semiconductor pattern,

wherein the first side surface of the lower portion of the third isolation pattern is aligned with the first side surface of the second isolation pattern, and

wherein the second side surface of the lower portion of the third isolation pattern is aligned with the second side surface of the second isolation pattern.

10. The image sensor of claim 7 , wherein the first material of the first isolation pattern is a first insulating material,

wherein the second material of the second isolation pattern is a second insulating material, and

wherein the third material of the third isolation pattern is a third insulating material.

11. An image sensor comprising:

a substrate comprising a plurality of pixel regions, the substrate having a first surface, a second surface opposite the first surface, a first trench recessed from the first surface;

a shallow device isolation pattern provided in the first trench and extending to a first level, and a second trench extending from the first level of the first trench to the second surface of the substrate; and

a deep device isolation pattern provided in the substrate between pixel regions of the plurality of pixel regions,

wherein the deep device isolation pattern comprises a semiconductor pattern penetrating at least a portion of the substrate, and an isolation pattern provided between the substrate and the semiconductor pattern,

wherein the isolation pattern comprises a first isolation pattern adjacent to the second surface of the substrate, and a second isolation pattern adjacent to the first surface of the substrate,

wherein the second isolation pattern comprises a lower portion provided under the shallow device isolation pattern and in the second trench, and an upper portion penetrating the shallow device isolation pattern and provided in the first trench and the second trench,

wherein the lower portion of the second isolation pattern is aligned with the first isolation pattern, and

wherein the first isolation pattern comprises a first material, and the second isolation pattern comprises a second material that is different from the first material.

12. The image sensor of claim 11 , wherein the first isolation pattern is spaced apart from the shallow device isolation pattern.

13. The image sensor of claim 11 , wherein a refractive index of the first material of the first isolation pattern is in a range from 1 to 2, and

wherein a dielectric constant of the second material of the second isolation pattern is in a range from 4 to 25.

14. The image sensor of claim 11 , wherein the first material of the first isolation pattern comprises silicon oxide, and

wherein the second material of the second isolation pattern comprises at least one of a nitride, a metal nitride, or a metal oxide.

15. The image sensor of claim 14 , wherein the second material of the second isolation pattern comprises at least one of tungsten or hafnium.

16. The image sensor of claim 11 , wherein a height of the first isolation pattern is greater than a height of the second isolation pattern.

17. The image sensor of claim 11 , wherein a height of the first isolation pattern ranges is in a range from 60% to 95% of a total height of the isolation pattern.

18. An image sensor comprising:

a substrate comprising a plurality of pixel regions, the substrate having a first surface, a second surface opposite the first surface, a first trench recessed from the first surface and extending to a first level, and a second trench extending from the first level of the first trench to the second surface of the substrate;

a shallow device isolation pattern provided in the first trench;

a deep device isolation pattern provided between pixel regions of the plurality of pixel regions and disposed in the substrate;

a transistor provided on the first surface of the substrate;

micro lenses provided on the second surface of the substrate; and

color filters provided on the plurality of pixel regions and between the substrate and the micro lenses,

wherein the deep device isolation pattern comprises a semiconductor pattern penetrating at least a portion of the substrate, and an isolation pattern provided between the substrate and the semiconductor pattern,

wherein the isolation pattern comprises a first isolation pattern adjacent to the second surface of the substrate, and a second isolation pattern adjacent to the first surface of the substrate, the second isolation pattern extending from the first trench into the second trench, and

wherein the first isolation pattern comprises a first insulating material and the second isolation pattern comprises a second insulating material that is different from the first insulating material.

19. The image sensor of claim 18 , wherein a height of the first isolation pattern is in a range from 3 times to 10 times a height of the second isolation pattern.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE FIFTH INVENTOR’S NAME AND EXECUTION DATE PREVIOUSLY RECORDED ON REEL 59463 FRAME 174. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNORS’ INTEREST. Recorded Mar 19, 2025
From: KIM, JUNGHYUN; KIM, BUMSUK; PARK, JONGHOON; YOO, HYUNGEUN; LEE, YUN KI
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 070565/0730 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2022
From: KIM, JUNGHYUN; KIM, BUMSUK; PARK, JONGHOON; YOO, HYUNGEUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 059463/0174 →
Priority Claims (1)
KR 10-2021-0098676 · Jul 27, 2021 · national
Continuity (1)
Related Publication 20230036152A1 · Feb 2, 2023
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