Display panel and manufacturing method thereof
View Patent ↗A display panel and a manufacturing method are provided. The present disclosure can reduce process steps of the display panel by disposing a first source electrode and a first drain electrode of a low temperature polysilicon thin film transistor and a second source electrode and a second drain electrode of an oxide thin film transistor in a same layer. Therefore, stability of the oxide thin film transistor can be improved, a channel length of the oxide thin film transistor can be shortened correspondingly, resolution of the display panel can be improved, and a thickness of the display panel can be reduced.
1. A display panel, comprising a plurality of gate lines and data lines arranged crosswise and insulated from each other to form a plurality of sub-pixels arranged in an array, wherein each of the sub-pixels is at least provided with a first thin film transistor, a second thin film transistor, a pixel capacitor, a power supply terminal, and a light-emitting unit;
wherein the first thin film transistor comprises a low temperature polysilicon thin film transistor, the low temperature polysilicon thin film transistor comprises a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode is connected to the pixel capacitor, and the first source electrode is connected to the power supply terminal, and the first drain electrode is connected to the light-emitting unit;
the second thin film transistor comprises an oxide thin film transistor, the oxide thin film transistor comprises a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode is connected to the gate lines, the second source electrode is connected to the data lines, and the second drain electrode is connected to the first gate electrode; and
the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed in a same layer, and the first source electrode and the first drain electrode are insulated from the second source electrode and the second drain electrode;
wherein the display panel further comprises a substrate, the low temperature polysilicon thin film transistor comprises a first active layer disposed on the substrate, the first gate electrode is disposed on one side of the first active layer, the first source electrode and the first drain electrode are disposed on one side of the first active layer away from the substrate, and the first source electrode and the first drain electrode are connected to the first active layer;
the oxide thin film transistor comprises a second active layer disposed on the substrate, the second gate electrode is disposed on one side of the second active layer away from the substrate, the second source electrode and the second drain electrode are disposed under the second active layer, and the second gate electrode is disposed on the side of the second active layer away from the second source electrode;
wherein the display panel further comprises:
a first gate insulating layer disposed on the side of the first active layer away from the substrate;
a first gate electrode layer disposed on one side of the first gate insulating layer away from the first active layer, wherein the first gate electrode layer comprises the first gate electrode;
an interlayer insulating layer disposed on one side of the first gate electrode layer away from the first gate insulating layer;
a source and drain electrode layer disposed on one side of the interlayer insulating layer away from the first gate electrode layer;
a first passivation layer disposed on one side of the source and drain electrode layer away from the interlayer insulating layer;
the second active layer disposed on one side of the first passivation layer away from the source and drain electrode layer;
a second gate insulating layer disposed on one side of the second active layer away from the first passivation layer;
a second gate electrode layer disposed on one side of the second gate insulating layer away from the second active layer, wherein the second gate electrode layer comprises the second gate electrode and the gate lines; and
a second passivation layer disposed on one side of the second gate electrode layer away from the second gate insulating layer;
wherein the source and drain electrode layer comprises the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, and the data lines;
wherein the first passivation layer is disposed on the first source electrode and the first drain electrode and extends above the second source electrode and the second drain electrode.
2. The display panel according to claim 1 , wherein a projection of the second gate electrode on the substrate and a projection of the second source electrode and the second drain electrode on the substrate have an overlapping portion, and an area of the overlapping portion is greater than or equal to a threshold value;
wherein the threshold value is 2 μm.
3. The display panel according to claim 1 , further comprising a buffer layer disposed between the substrate and the first active layer.
4. The display panel according to claim 3 , wherein a material of the buffer layer comprises silicon oxide, silicon nitride, silicon oxynitride, a laminate of silicon oxide and silicon nitride, or a mixed material.
5. The display panel according to claim 1 , wherein a material of the first active layer comprises polysilicon.
6. The display panel according to claim 1 , wherein a material of the first gate electrode layer comprises molybdenum, a laminate of molybdenum/aluminum, a laminate of molybdenum/copper, a laminate of molybdenum-titanium alloy/copper, a laminate of titanium/aluminum/titanium, a laminate of titanium/copper/titanium, a laminate of molybdenum/copper/indium zinc oxide, a laminate of indium zinc oxide/copper/indium zinc oxide, a laminate of molybdenum/copper/indium tin oxide, a laminate of nickel/copper/nickel, a laminate of molybdenum-nickel-titanium alloy/copper/molybdenum-nickel-titanium alloy, nickel-chromium alloy/copper/nickel-chromium alloy, titanium-nickel alloy/copper/titanium-nickel alloy, a laminate of titanium-chromium alloy/copper/titanium-chromium alloy, or niobium-copper alloy.
7. The display panel according to claim 1 , wherein the low temperature polysilicon thin film transistor comprises N-type transistors and P-type transistors.
8. The display panel according to claim 1 , wherein a material of the interlayer insulating layer comprises silicon oxide, silicon nitride, or silicon oxynitride.
9. The display panel according to claim 1 , wherein a material of the source and drain electrode layer comprises molybdenum, a laminate of molybdenum/aluminum, a laminate of molybdenum/copper, a laminate of molybdenum-titanium alloy/copper, a laminate of molybdenum-titanium alloy/copper/molybdenum-titanium alloy, a laminate of titanium/aluminum/titanium, a laminate of titanium/copper/titanium, a laminate of molybdenum/copper/indium zinc oxide, a laminate of indium zinc oxide/copper/indium zinc oxide, a laminate of molybdenum/copper/indium tin oxide, a laminate of nickel/copper/nickel, a laminate of molybdenum-nickel-titanium alloy/copper/molybdenum-nickel-titanium alloy, nickel-chromium alloy/copper/nickel-chromium alloy, titanium-nickel alloy/copper/titanium-nickel alloy, a laminate of titanium-chromium alloy/copper/titanium-chromium alloy, or niobium-copper alloy.
10. The display panel according to claim 1 , wherein a material of the first passivation layer comprises silicon oxide, a laminate of silicon oxide/silicon nitride, or a laminate of aluminum oxide/silicon oxide.
11. The display panel according to claim 1 , wherein a material of the second active layer comprises indium gallium zinc oxide, indium gallium tin oxide, indium gallium oxide, indium zinc oxide, zinc aluminum oxide, or zinc aluminum tin oxide.
12. The display panel according to claim 1 , wherein the pixel capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate and the first gate electrode are disposed in a same layer, and the second electrode plate and the second gate electrode are disposed in another same layer.
13. The display panel according to claim 1 , wherein the pixel capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate and the second source electrode are disposed in a same layer, and the second electrode plate and the second gate electrode are disposed in another same layer.