Semiconductor device
A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
1. A semiconductor device, comprising:
a substrate having an array region defined thereon;
magnetic tunneling junction (MTJ) patterns on the array region, wherein the MTJ patterns are arranged in an array;
a ring of dummy pattern surrounding the array region, wherein the ring of dummy pattern comprises:
a ring of MTJ pattern surrounding the array region, wherein the ring of MTJ pattern is made of a single MTJ; and
a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
2. The semiconductor device of claim 1 , further comprising a gap between the array region and the ring of dummy pattern.
3. The semiconductor device of claim 1 , wherein the ring of MTJ pattern comprises:
a first MTJ pattern and a second MTJ pattern extending along a first direction; and
a third MTJ pattern and a fourth MTJ pattern extending along a second direction.
4. The semiconductor device of claim 3 , wherein the first MTJ pattern overlaps the third MTJ pattern at a first corner, the first MTJ pattern overlaps the fourth MTJ pattern at a second corner, the second MTJ pattern overlaps the third MTJ pattern at a third corner, and the second MTJ pattern overlaps the fourth MTJ pattern at a fourth corner.
5. The semiconductor device of claim 1 , wherein the ring of metal interconnect pattern comprises:
a first metal interconnect pattern and a second metal interconnect pattern extending along a first direction; and
a third metal interconnect pattern and a fourth metal interconnect pattern extending along a second direction.
6. The semiconductor device of claim 5 , wherein the first metal interconnect pattern overlaps the third metal interconnect pattern at a first corner, the first metal interconnect pattern overlaps the fourth metal interconnect pattern at a second corner, the second metal interconnect pattern overlaps the third metal interconnect pattern at a third corner, and the second metal interconnect pattern overlaps the fourth metal interconnect pattern at a fourth corner.