Systems and methods for isolating an accelerated function unit and/or an accelerated function context
Systems, methods, and devices for isolating a misbehaving accelerator circuit, such as an accelerator function unit or an accelerated function context, are provided. An integrated circuit may include a region that includes an accelerator circuit. When the accelerator circuit issues a request, another region of the integrated circuit or a processor connected to the integrated circuit may determine whether there is a misbehavior associated with the request and, in response to determining that there is a misbehavior associated with the request, may perform a misbehavior response to mitigate a negative impact of the misbehavior of the accelerator circuit.
1. An integrated circuit device comprising:
a user partition of programmable logic circuitry reconfigurable during runtime with a user-defined accelerator; and
a static partition of programmable logic circuitry not to be reconfigured during runtime, wherein the static partition is to isolate the user-defined accelerator in response to identifying a protocol violation in a communication of the user-defined accelerator.
2. The integrated circuit device of claim 1 , wherein the protocol comprises an Advanced Extensible Interface (AXI) protocol.
3. The integrated circuit device of claim 1 , wherein the user-defined accelerator communicates via a physical function.
4. The integrated circuit device of claim 1 , wherein the protocol violation in the communication comprises an incorrectly formatted communication.
5. The integrated circuit device of claim 4 , wherein the communication comprises a physical function (PF) request.
6. The integrated circuit device of claim 1 , wherein the protocol violation in the communication comprises an incorrectly formatted data packet.
7. The integrated circuit device of claim 1 , wherein the protocol violation in the communication comprises a lack of response by the user-defined accelerator to a read request.
8. An article of manufacture comprising one or more tangible, non-transitory machine-readable media comprising instructions that, when executed by a data processing system, cause the data processing system to generate a programmable logic device system design comprising:
an accelerator to be configured in a reconfigurable region of the programmable logic device to be reconfigurable during runtime; and
error detection and mitigation logic to be configured in a static region of the programmable logic device not to be reconfigurable during runtime, wherein the error detection and mitigation logic is to check compliance of a logical protocol interface transaction of the accelerator.
9. The article of manufacture of claim 8 , wherein the error detection and mitigation logic is to check compliance of the logical protocol interface transaction, wherein the logical protocol interface transaction originates from the accelerator.
10. The article of manufacture of claim 8 , wherein the error detection and mitigation logic is to check compliance with an Advanced Extensible Interface (AXI) protocol of the logical protocol interface transaction.
11. The article of manufacture of claim 8 , wherein the error detection and mitigation logic is to isolate the accelerator based on noncompliance of the logical protocol interface transaction.
12. The article of manufacture of claim 11 , wherein noncompliance of the logical protocol interface transaction comprises a data packet that is incorrectly formatted.
13. The article of manufacture of claim 8 , wherein noncompliance of the logical protocol interface transaction comprises a failure to respond to a request.
14. The article of manufacture of claim 8 , wherein all communication by the accelerator passes through the static region of the programmable logic device.
15. The article of manufacture of claim 14 , wherein all communication by the accelerator is subject to the error detection and mitigation logic.
16. An integrated circuit device comprising:
a reconfigurable region of programmable logic circuitry configurable during runtime to be programmed with a user-defined accelerator; and
a static region of programmable logic circuitry not to be reconfigured during runtime, wherein the static region is to mitigate misbehavior by the user-defined accelerator, wherein the misbehavior comprises noncompliant communication.
17. The integrated circuit device of claim 16 , wherein the noncompliant communication comprises a protocol-noncompliant communication.
18. The integrated circuit device of claim 17 , wherein the protocol-noncompliant communication comprises Advanced Extensible Interface (AXI)-noncompliant communication.
19. The integrated circuit of claim 16 , wherein the noncompliant communication comprises a failure to respond to a request.
20. The integrated circuit of claim 19 , wherein the request comprises a memory-mapped input/output (MMIO) read request.