Write merging on stores with different privilege levels
A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.
1. A device comprising:
a processor configured to perform a first set of instructions associated with a first privilege level and a second set of instructions associated with a second privilege level;
a cache controller coupled to the processor;
a cache memory coupled to the cache controller and that includes a cache line; and
a second memory coupled to the cache controller, wherein the cache controller is configured to:
receive a write command associated with writing a first set of data to the cache line, wherein the first set of data is associated with the first privilege level; and
based on the write command:
determine whether the cache line currently stores a second set of data associated with the second privilege level; and
when the cache line stores the second set of data:
merge the first set of data with the second set of data to produce a merged set of data;
store the merged set of data in the cache line;
determine a merged indicator that specifies a third privilege level associated with the merged set of data; and
store the merged indicator in the second memory.
2. The device of claim 1 , wherein the second memory is configured to store state data associated with the cache line.
3. The device of claim 2 , wherein the state data specifies whether a value stored in the cache line is modified, exclusive, shared, or invalid.
4. The device of claim 1 further comprising a third memory coupled to the cache controller and configured to store a table, wherein the cache controller is configured to determine the merged indicator based on the table.
5. The device of claim 4 , wherein the table is configurable.
6. The device of claim 1 , wherein each of the first privilege level and the second privilege level includes two parts.
7. The device of claim 6 , wherein each of the first privilege level and the second privilege level includes a first part that specifies either a guest privilege or a root privilege.
8. The device of claim 7 , wherein each of the first privilege level and the second privilege level includes a second part that specifies either a user privilege or a supervisor privilege.
9. The device of claim 1 , wherein the third privilege level is a lower of the first privilege level and the second privilege level.
10. The device of claim 1 , wherein the cache memory is a victim cache memory, and the second memory is a victim cache tag memory.
11. The device of claim 10 , further comprising a main cache memory coupled to the cache controller, wherein the victim cache memory is configured to store data evicted from the main cache memory.
12. The device of claim 1 , wherein the cache controller is a level one (L1) cache controller, and the cache memory is an L1 cache memory.
13. A device comprising:
a processor configured to perform a first process associated with a first privilege level and a second process associated with a second privilege level;
a cache controller coupled to the processor;
a main cache memory;
a victim cache memory coupled to the cache controller and that includes a cache line; and
a third memory coupled to the cache controller, wherein the cache controller is configured to:
receive, from the processor, a write command associated with writing a first set of data at an address, wherein the first set of data is associated with the first process; and
based on the write command:
determine whether data associated with the address is stored in the main cache memory or stored in the victim cache memory in parallel; and
determine, based on whether the cache line of the victim cache memory currently stores a second set of data associated with the second process, whether to:
merge the first set of data with the second set of data to produce a merged set of data;
store the merged set of data in the cache line;
determine a merged indicator that specifies a third privilege level associated with the merged set of data; and
store the merged indicator in the third memory.
14. The device of claim 13 , wherein the third memory is configured to store state data associated with the cache line.
15. The device of claim 14 , wherein the state data specifies whether a value stored in the cache line is modified, exclusive, shared, or invalid.
16. The device of claim 13 further comprising a fourth memory coupled to the cache controller and configured to store a table, wherein the cache controller is configured to determine the merged indicator based on the table.
17. A method comprising:
receiving a write command associated with writing a first set of data to a cache line of a cache memory, wherein the first set of data is associated with a first privilege level;
determining whether a second set of data is stored in the cache line, wherein the second set of data is associated with a second privilege level; and
determining, based on whether the second set of data is stored in the cache line, whether to:
merge the first set of data with the second set of data to produce a merged set of data;
store the merged set of data in the cache line;
determine a merged indicator that specifies a third privilege level associated with the merged set of data; and
store the merged indicator in a second memory.
18. The method of claim 17 , wherein the second memory is configured to store state data associated with the cache line.
19. The method of claim 18 , wherein the state data specifies whether a value stored in the cache line is modified, exclusive, shared, or invalid.
20. The method of claim 17 , wherein the determining of the merged indicator includes querying a table based on the first privilege level and the second privilege level.