Tile sequencing mechanism
An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
1. A graphics processing unit (GPU), comprising:
a cache memory to store object data and associated control data for objects to be rendered via tile-based rendering;
sequencer circuitry to generate a plurality of batches of objects to be rendered, determine tiles intersected by objects in each of the plurality of batches, and select, based on the tiles intersected by objects, a cache aware tile walk pattern; and
rasterization circuitry to walk lit tiles according to the cache aware tile walk pattern and process primitive commands for objects in the plurality of batches of objects that are associated with the tiles intersected by the objects.
2. The GPU of claim 1 , wherein the sequencer circuitry is to size the plurality of batches according to a size of the cache memory.
3. The GPU of claim 2 , wherein to generate the plurality of batches, the sequencer circuitry is to collect objects in a sequential order until a batch closing condition has been detected.
4. The GPU of claim 3 , wherein the batch closing condition includes at least one of a maximum batch size being accumulated and detection of one or more asynchronous conditions.
5. The GPU of claim 1 , wherein the objects are to be rendered via tile-based immediate mode rendering.
6. The GPU of claim 1 , wherein the rasterization circuitry to walk lit tiles according to the cache aware tile walk pattern for a first batch of the plurality of batches in parallel with determination of tiles intersected by objects in a second batch of the plurality of batches by the sequencer circuitry.
7. The GPU of claim 1 , wherein the sequencer circuitry includes mode control circuitry configured to determine a mode of operation of the sequencer circuitry to render the plurality of batches of objects.
8. The GPU of claim 7 , wherein the mode control circuitry is configured to receive mode control information that indicates whether the sequencer circuitry is to operate in tile mode or an in-order mode.
9. A method to facilitate graphics rendering, comprising:
storing object data and associated control data for objects to be rendered via tile-based rendering to a cache memory;
generating a plurality of batches of objects to be rendered via sequencer circuitry;
determining tiles intersected by objects in each of the plurality of batches via sequencer circuitry and selecting, via the sequencer circuitry and based on the tiles intersected by objects, a cache aware tile walk pattern;
walking lit tiles via rasterization circuitry according to the cache aware tile walk pattern; and
processing, via the rasterization circuitry, primitive commands for objects in the plurality of batches of objects that are associated with the tiles intersected by the objects.
10. The method of claim 9 , further comprising sizing the plurality of batches according to a size of the cache memory via the sequencer circuitry.
11. The method of claim 10 , wherein generating the plurality of batches includes collecting objects in a sequential order until a batch closing condition has been detected.
12. The method of claim 11 , wherein the batch closing condition includes at least one of a maximum batch size being accumulated and detection of one or more asynchronous conditions.
13. The method of claim 9 , further comprising rendering the objects via tile-based immediate mode rendering.
14. The method of claim 9 , further comprising walking lit tiles according to the cache aware tile walk pattern for a first batch of the plurality of batches in parallel with determination of tiles intersected by objects in a second batch of the plurality of batches by the sequencer circuitry.
15. The method of claim 9 , further comprising determine, via mode control circuitry, a mode of operation of the sequencer circuitry to render the plurality of batches of objects, including receiving mode control information that indicates whether the sequencer circuitry is to operate in tile mode or an in-order mode.
16. A graphics processing system comprising:
a memory device; and
a graphics processor coupled with the memory device, the graphics processor including:
a cache memory to store object data and associated control data for objects to be
rendered via tile-based rendering;
sequencer circuitry to generate a plurality of batches of objects to be rendered, determine tiles intersected by objects in each of the plurality of batches, and select, based on the tiles intersected by objects, a cache aware tile walk pattern; and
rasterization circuitry to walk lit tiles according to the cache aware tile walk pattern and process primitive commands for objects in the plurality of batches of objects that are associated with the tiles intersected by the objects.
17. The graphics processing system of claim 16 , wherein the sequencer circuitry is to size the plurality of batches according to a size of the cache memory.
18. The graphics processing system of claim 17 , wherein to generate the plurality of batches, the sequencer circuitry is to collect objects in a sequential order until a batch closing condition has been detected.
19. The graphics processing system of claim 18 , wherein the batch closing condition includes at least one of a maximum batch size being accumulated and detection of one or more asynchronous conditions.
20. The graphics processing system of claim 19 , wherein the objects are to be rendered via tile-based immediate mode rendering.