Pixel circuit for forming slim bezel and display device including the same
A pixel circuit and a display device including the same are disclosed. The pixel circuit includes: a driving transistor which includes a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, and supplies a driving current to a light emitting device; a first transistor that is electrically connected between the first node and the second node; a second transistor that is electrically connected between the first node and a data voltage; a third transistor that is electrically connected between the first node and a power supply line that supplies a high potential voltage; and a storage capacitor that includes a first electrode connected to the high potential voltage and a second electrode connected to the second node.
1. A display panel comprising: a driving transistor including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, the driving transistor configured to supply a driving current to a light emitting device including an anode electrode, a cathode electrode, and an organic compound layer; a first transistor that is electrically connected between the second node and the third node; a second transistor that is electrically connected between the first node and a data line that supplies a data voltage; a third transistor that is electrically connected between the first node and a power line that supplies a high potential voltage; a storage capacitor which comprises a first electrode and a second electrode, the first electrode of the storage capacitor connected to the power line that supplies the high potential voltage and the second electrode of the storage capacitor connected to the second node; a fourth transistor electrically connected between the third node and a fourth node, the fourth node connected to the light emitting device; a sixth transistor electrically connected between the fourth node and a first voltage line that supplies an anode reset voltage; a seventh transistor electrically connected between the first node and a second voltage line that supplies a bias voltage, and a fifth transistor electrically connected between the second node and a voltage line that supplies an initialization voltage, and wherein the display panel is divided into a display area in which pixels are disposed, a first bezel area located on a first side of the display area, and a second bezel area located on a second side of the display area, and wherein a first gate-in-panel (GIP) driving circuit located on the first bezel area and a second GIP driving circuit located on the second bezel area are asymmetrical, and wherein the first GIP driving circuit comprises a light emission control (EM) driving circuit that supplies a light emission control signal to a pixel circuit, and the second GIP driving circuit does not comprise an EM driving circuit.
2. The display panel of claim 1 , wherein the first transistor and the second transistor receive a first scan signal, and the first transistor is configured to electrically connect the second electrode of the driving transistor to the gate electrode of the driving transistor responsive to the first scan signal, and the second transistor is configured to supply the data voltage to the first electrode of the driving transistor responsive to the first scan signal.
3. The display panel of claim 2 , wherein the third transistor and the fourth transistor receive the light emission control signal, and the third transistor is configured to apply the high potential voltage to the first node responsive to the light emission control signal and the fourth transistor is configured to electrically connect the second electrode of the driving transistor to the light emitting device at the fourth node.
4. The display panel of claim 3 , wherein the sixth transistor and the seventh transistor receive a third scan signal, and the sixth transistor is configured to apply the anode reset voltage to the light emitting device responsive to the third scan signal and the seventh transistor is configured to apply the bias voltage to the first electrode of the driving transistor responsive to the third scan signal.
5. The display panel of claim 2 , wherein the pixel circuit is arranged in a form of a matrix on a display panel, and the fifth transistor of the pixel circuit arranged in an n-th row (n is a natural number) receives the first scan signal which is input to the pixel circuit arranged in an (n-k)-th row (k is a natural number less than n), and supplies the initialization voltage to the gate electrode of the driving transistor responsive to the first scan signal that is also input to the pixel circuit in the (n-k)-th row.
6. The display panel of claim 5 , wherein at least one of the first transistor, the second transistor, and the fifth transistor is an oxide semiconductor transistor which comprises an oxide semiconductor material in an active layer.