Mixed material power devices and driver circuits
A power integrated circuit comprising: a heterojunction structure Gallium Nitride, GaN, chip comprising at least one GaN layer and at least one Aluminium Gallium Nitride, AlGaN, layer wherein the GaN chip comprises at least one main power device comprising a source terminal, a drain terminal, a gate terminal and a two-dimensional electron gas, 2DEG, formed at an interface between the AlGaN and GaN layers and between the source and drain terminals, wherein the gate terminal is configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal, a driver comprising at least one low-side component and at least one high-side component, wherein the low-side component comprises a terminal connected to a low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device; wherein the high-side component comprises at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device; wherein the at least one low-side component of the driver is configured to discharge an input capacitance of the main power device during a turn-off of the main power device and is monolithically integrated within the GaN chip; and wherein the at least one high-side component of the driver is configured to charge up the input capacitance of the main power device and is formed in a semiconductor region comprising a material other than GaN.
1. A power integrated circuit comprising:
a heterojunction structure Gallium Nitride, GaN, chip comprising at least one GaN layer and at least one Aluminium Gallium Nitride, AlGaN, layer wherein the GaN chip comprises at least one main power device comprising a source terminal, a drain terminal, a gate terminal and a two-dimensional electron gas, 2 DEG, formed at an interface between the AlGaN and GaN layers and between the source and drain terminals, wherein the gate terminal is configured to modulate at least a portion of the 2 DEG when a charge is applied to the gate terminal;
a driver comprising at least one low-side component and at least one high-side component, wherein the low-side component comprises a terminal connected to a low DC voltage rail and at least one other terminal connected to the gate terminal of the main power device; wherein the high-side component comprises at least one terminal connected to a high DC voltage rail and at least one other terminal connected to the gate of the main power device;
wherein the at least one low-side component of the driver is configured to discharge an input capacitance of the main power device during a turn-off of the main power device and is monolithically integrated within the GaN chip;
wherein the at least one high-side component of the driver is configured to charge up the input capacitance of the main power device and is formed in a semiconductor region comprising a material other than GaN; and
wherein the at least one high-side component of the driver is provided in a first semiconductor material, the at least one low-side component of the driver is provided in a second semiconductor material, and wherein the first semiconductor material and the second semiconductor material are different semiconductor materials.
2. A power integrated circuit according to claim 1 , wherein the at least one other terminal of the high-side component connected to the gate of the main power device is connected indirectly to the gate of the main power device through a diode and/or a resistor.
3. A power integrated circuit according to claim 1 , wherein the main power device and/or the low-side component of the driver is a High Electron Mobility Transistor (HEMT), and wherein the main power device has a higher power output and a higher blocking voltage than the low-side component of the driver.
4. A power integrated circuit according to claim 1 , wherein the main power device and/or the low-side component of the driver comprises a plurality of 2DEG channels arranged in parallel between the source and drain terminals of the main power device.
5. A power integrated circuit according to claim 4 , wherein the low-side component of the driver is configured to provide an increased resistance when the low-side component of the driver is in an OFF state and a reduced resistance when the low-side component of the driver is in an ON-state.
6. A power integrated circuit according to claim 1 , wherein the low-side component of the driver comprises one of: a HEMT, MOSFET or MISFET, operative as a Miller clamp with a drain terminal connected to the gate terminal of the main power device and a source connected to the source of the main power device, and
wherein the low-side component can be arranged proximal to the main power device or within a structure of the main power device.
7. A power integrated circuit according to claim 6 , wherein the low-side component of the driver comprises said HEMT, the HEMT comprises multiple p+ GaN islands displaced in a direction perpendicular to the current flow between the source and drain terminals of said HEMT and wherein all the p+ multiple GaN islands are connected to the gate terminal of the said HEMT.
8. A power integrated circuit according to claim 1 , wherein the at least low-side component of the driver comprises a normally-on or normally-off transistor or a parallel combination of a normally-on and normally-off transistor.
9. A power integrated circuit according to claim 1 , wherein the GaN chip comprises one or more further 2DEG low-power transistors connected to the main power device or the low-side component of the driver.
10. A power integrated circuit according to claim 1 , wherein the at least one high-side component of the driver is configured as a hole conduction component and/or is a p-channel MOSFET and/or is a bipolar NPN transistor.
11. A power integrated circuit according to claim 1 , wherein the at least one high-side component of the driver and the at least one low-side component of the driver operate as a CMOS cell.
12. A power integrated circuit according to claim 1 wherein a further low-side component of the driver is arranged in parallel with the at least one low-side component of the driver and provided in the semiconductor region comprising a material other than GaN.
13. A power integrated circuit according to claim 12 , wherein the further low-side component of the driver comprises an n-channel MOSFET, an n-channel JFET, a PNP bipolar transistor or an NPN transistor with an additional inverter placed on a base terminal of the NPN transistor.
14. A power integrated circuit according to claim 1 , wherein the GaN chip comprises one or more current sensing devices or high voltage current sensing switches configured for current sensing.
15. A power integrated circuit according to claim 1 , wherein the semiconductor region comprising a material other than GaN is formed on a semiconductor substrate and positioned below or adjacent and below a heterojunction interface of the GaN chip, and wherein the substrate comprises a silicon or silicon carbide material.
16. A power integrated circuit comprising:
at least one heterojunction structure Gallium Nitride, GaN, chip comprising at least one GaN layer and at least one Aluminium Gallium Nitride, AlGaN, layer wherein the GaN chip comprises at least one main power device comprising a source terminal, a drain terminal, a gate terminal, and a two-dimensional electron gas, 2DEG, formed at an interface between the AlGaN and GaN layers and between the source and drain terminals, wherein the gate terminal is configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal;
a half bridge circuit comprising a low-side main power device formed in the at least one GaN chip, a high-side main power device formed in the at least one GaN chip or in a further GaN chip;
a driver containing a first pair and a second pair, each pair comprising at least one low-side component and at least one high side component, wherein the first pair is configured to charge and discharge the input capacitance of the low-side main power device during the turn-on and turn-off of the low-side main power device, and wherein the second pair is configured to charge and discharge the input capacitance of the high-side main power device during the turn-on and turn-off of the low-side main power device;
wherein the driver further comprises a level shifter configured to shift the low voltage control of the first pair to a high voltage control of the second pair,
wherein each of the at least one low-side component of the driver is formed in the GaN chip or in the further GaN chip; and
wherein each of the at least one high-side component of the driver are formed in a semiconductor region comprising a material other than GaN.
17. A power integrated circuit comprising:
a plurality of heterojunction structure Gallium Nitride, GaN, chips each comprising at least one, GaN, layer and at least one Aluminium Gallium Nitride, AlGaN, layer wherein each of the GaN chips comprises at least one main power device comprising a source terminal, a drain terminal, a gate terminal and a two-dimensional electron gas, 2DEG, formed at an interface between the AlGaN and GaN layers and between the source and drain terminals, wherein the gate terminal is configured to modulate at least a portion of the 2DEG when a charge is applied to the gate terminal,
wherein each of the GaN chips comprises a low-side component of a driver;
wherein the main power devices of the plurality of GaN chips are connected in parallel; and
a single silicon companion chip comprising at least one high-side component of the driver, wherein the at least one-high side component of the driver is connected to the drain terminals of the low-side components of the main power devices of the plurality of GaN chips and is further connected to the gate terminals of the main power devices of the plurality of GaN chips.
18. A power integrated circuit according to claim 17 wherein the semiconductor region comprising a material other than GaN comprises a silicon companion chip configured for one of: CMOS operation, high voltage CMOS operation, bipolar CMOS operation, bipolar CMOS operation, DMOS (BCD) operation.
19. A power integrated circuit according to claim 17 wherein the single silicon companion chip comprises one or more of:
a level shifter;
a logic circuit;
a voltage regulator;
a start-up circuits;
a bandgap reference;
current sensing, current amplifier or transconductance circuits;
temperature sensing;
an over-current and an over-temperature protection circuit;
a memory storage;
an under-voltage lock-out circuit;
a slew rate control circuit;
an electrostatic discharge, ESD, protection device; and
a PWM controller.