IP Library Granted Patent US 12,294,798
Granted Patent B2
US 12,294,798 · App. 18/406,432 · Granted May 6, 2025

Photoelectric conversion device, photoelectric conversion system, and moving body

Inventors: Hideo Kobayashi (Tokyo, JP); Daisuke Yoshida (Kanagawa, JP)
Assignee: Canon Kabushiki Kaisha
H04N25/75H04N25/766H04N25/772H04N25/778
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Quick Facts
Patent No.
US 12,294,798
App. No.
18/406,432
Granted
May 6, 2025
Kind
B2
Abstract

A photoelectric conversion device includes a pixel array and a reading unit including a plurality of reading circuits each configured to read a signal from the pixel array. Each reading circuit includes a sample-and-hold unit including a first sample-and-hold circuit configured to hold a reset level output from the pixel array and a second sample-and-hold circuit configured to hold a photo signal level output from the pixel array. The plurality of reading circuits include first reading circuits forming a first group and second reading circuits forming a second group. At least some of the plurality of first reading circuits are controlled by a first control signal given via a first control line, and at least some of the plurality of second reading circuits are controlled by a second control signal given via a second control line.

Claims (41)

1. A photoelectric conversion device comprising:

a pixel array including a plurality of pixels arranged to form a plurality of rows and a plurality of columns; and

a reading unit including a plurality of reading circuits each configured to read a signal from the pixel array,

wherein each of the plurality of reading circuits includes a sample-and-hold unit, the sample-and-hold unit including (1) a first sample-and-hold circuit configured to hold a reset level output from the pixel array and (2) a second sample-and-hold circuit configured to hold a photo signal level output from the pixel array,

wherein the plurality of reading circuits include (1) a plurality of first reading circuits forming a first group and (2) a plurality of second reading circuits forming a second group, wherein the first sample and hold circuit and the second sample and hold circuit included in one of the plurality of first reading circuits are controlled by a first control signal given via a first control line, and

wherein the first sample and hold circuit and the second sample and hold circuit included in one of the plurality of second reading circuits are controlled by a second control signal given via a second control line.

2. The device according to claim 1 , wherein the photoelectric conversion device has a plurality of operation modes, and

wherein the plurality of operation modes include modes in which an active period of the first control signal and an active period of the second control signal are different from each other.

3. The device according to claim 1 , further comprising a generator circuit configured to generate the first control signal and the second control signal.

4. The device according to claim 1 , further comprising a first pad and a second pad which are configured to receive the first control signal and the second control signal from the outside, respectively.

5. The device according to claim 1 , wherein the first control signal is a signal for setting the plurality of first reading circuits in one of a plurality of states including a first state and a second state,

wherein the second control signal is a signal for setting the plurality of second reading circuits in one of the plurality of states, and

wherein the second state is a state in which power consumption is lower than in the first state.

6. The device according to claim 1 , wherein each of the plurality of reading circuits further includes an AD converter configured to AD-convert a signal provided from the sample-and-hold unit.

7. The device according to claim 6 , wherein the AD converter includes a delta-sigma AD converter.

8. The device according to claim 7 , wherein each of the plurality of first reading circuits includes a potential fixing device configured to fix a potential of an input node of the delta-sigma AD converter in accordance with the first control signal, and

wherein each of the plurality of second reading circuits includes a potential fixing device configured to fix a potential of an input node of the delta-sigma AD converter in accordance with the second control signal.

9. The device according to claim 6 , wherein the reading unit includes a switching circuit configured to supply an output from each sample-and-hold unit to at least two AD converters.

10. The device according to claim 1 , wherein the reading unit is configured to generate a signal corresponding to a signal of a pixel assigned with one of the plurality of first reading circuits and a signal of a pixel assigned with one of the plurality of second reading circuits.

11. The device according to claim 1 , wherein the reading unit further includes:

a first switch configured to electrically connect an output of the first sample-and-hold circuit of one of the plurality of first reading circuits and an output of the first sample-and-hold circuit of one of the plurality of second reading circuits; and

a second switch configured to electrically connect an output of the second sample-and-hold circuit of one of the plurality of first reading circuits and an output of the second sample-and-hold circuit of one of the plurality of second reading circuits.

12. The device according to claim 11 , wherein the sample-and-hold unit includes a resistive element configured to connect the output of the first sample-and-hold circuit and the output of the second sample-and-hold circuit.

13. The device according to claim 1 , wherein the reading unit includes a circuit configured to average an output from one of the plurality of first reading circuits and an output from one of the plurality of second reading circuits.

14. The device according to claim 1 , wherein the first sample-and-hold circuit includes a first capacitive element and a first amplifier, and

wherein the second sample-and-hold circuit includes a second capacitive element and a second amplifier.

15. A photoelectric conversion system comprising:

a photoelectric conversion device according to claim 1 ; and

a signal processor configured to process a signal output from the photoelectric conversion device.

16. A moving body comprising:

a photoelectric conversion device according to claim 1 ; and

a signal processor configured to process a signal output from the photoelectric conversion device.

17. A substrate comprising:

a reading unit including a plurality of reading circuits each configured to read a signal from a pixel array including a plurality of pixels,

wherein each of the plurality of reading circuits includes a sample-and-hold unit, the sample-and-hold unit including (1) a first sample-and-hold circuit configured to hold a reset level output from the pixel array and (2) a second sample-and-hold circuit configured to hold a photo signal level output from the pixel array,

wherein the plurality of reading circuits include (1) a plurality of first reading circuits forming a first group and (2) a plurality of second reading circuits forming a second group,

wherein the first sample and hold circuit and the second sample and hold circuit included in one of the plurality of first reading circuits, are controlled by a first control signal given via a first control line and

wherein the first sample and hold circuit and the second sample and hold circuit included in one of the plurality of second reading circuits are controlled by a second control signal given via a second control line.

18. The device according to claim 1 , wherein the one of the plurality of first reading circuits and the one of the plurality of second reading circuits are arranged to be adjacent to each other.

19. The device according to claim 1 , wherein the first control line and the second control line pass through the plurality of reading circuits.

20. The device according to claim 1 , wherein a number of the plurality of first reading circuits controlled by the first control signal given via the first control line and a number of the plurality of second reading circuits controlled by the second control signal given via the second control line are the same.

Priority Claims (1)
JP 2021-045158 · Mar 18, 2021 · national
Continuity (2)
Continuation 17690236 · Mar 9, 2022
Related Publication 20240147096A1 · May 2, 2024
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