Component carrier with partially metallized hole using anti-plating dielectric structure and electroless plateable separation barriers
A component carrier includes a stack with at least one electrically conductive layer structure, at least one electrically insulating layer structure, and a hole in the stack having a first hole portion covered with metal and having a second hole portion not covered with metal, wherein the second hole portion is defined by an anti-plating dielectric structure and an electroless plateable separation barrier.
1. A component carrier, comprising:
a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; and
a hole in the stack having a first hole portion covered with metal and having a second hole portion not covered with metal;
wherein the second hole portion is defined by an anti-plating dielectric structure and an electroless plateable separation barrier,
wherein the second hole portion extends upwardly from the anti-plating dielectric structure up to an upper main surface of the stack.
2. The component carrier according to claim 1 , wherein the first hole portion is continuously lined with the metal.
3. The component carrier according to claim 1 , wherein the anti-plating dielectric structure is embedded in the stack and is exposed only at an interface between the first hole portion and the second hole portion.
4. The component carrier according to claim 1 , wherein the separation barrier is located at a main surface of the stack.
5. The component carrier according to claim 1 , wherein the anti-plating dielectric structure comprises a planar pad.
6. The component carrier according to claim 1 , wherein the anti-plating dielectric structure comprises an inlay.
7. The component carrier according to claim 1 , wherein the anti-plating dielectric structure is formed on a metallic pad connected to a metallic trace.
8. The component carrier according to claim 1 , wherein the separation barrier comprises an annular metal-free region on a main surface of the stack, delimited at an exterior side by a metallic structure.
9. The component carrier according to claim 1 , comprising an electrically conductive ring structure connected with the anti-plating dielectric structure.
10. The component carrier according to claim 9 , wherein the electrically conductive ring structure is connected with the metal.
11. The component carrier according to claim 1 , wherein the anti-plating dielectric structure is hydrophobic.
12. The component carrier according to claim 1 , wherein the anti-plating dielectric structure comprises at least one of a group consisting of a release ink, polytetrafluoroethylene, and polyimide.
13. The component carrier according to claim 1 , wherein the hole has a substantially constant diameter in the first hole portion and in the second hole portion.
14. The component carrier according to claim 1 , wherein a vertical thickness of the anti-plating dielectric structure is in a range from 10 μm to 50 μm.
15. The component carrier according to claim 1 , wherein the metal in the first hole portion extends up to and along at least part of a main surface of the stack.
16. The component carrier according to claim 1 , comprising at least one of the following features:
the component carrier is configured as stub-less radiofrequency component carrier;
wherein the second hole portion extends between the anti-plating dielectric structure and the separation barrier;
wherein the anti-plating dielectric structure comprises a dielectric ring structure; comprising only a single anti-plating dielectric structure;
wherein the anti-plating dielectric structure separates the second hole portion from the metal covering the first hole portion;
wherein the separation barrier separates the second hole portion from a metallic structure outside of the hole, wherein the metallic structure is a multi-layer structure;
wherein the separation barrier is not electro-plateable;
wherein the second hole portion is electrically isolated by and between the anti-plating dielectric structure and the separation barrier;
wherein the hole is a vertical hole.
17. A method of manufacturing a component carrier, comprising:
providing a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure;
forming a hole in the stack with a first hole portion covered with metal and with a second hole portion not covered with metal;
defining the second hole portion by an anti-plating dielectric structure and an electroless plateable separation barrier; and
wherein the second hole portion extends from the anti-plating dielectric structure to a main surface of the stack.
18. The method according to claim 17 , comprising at least one of the following features:
wherein the method comprises forming the separation barrier by lithography;
wherein the method comprises forming the separation barrier as an annular dielectric surface area on a main surface of the stack delimited at an exterior side by a metallic structure on the main surface and delimited at an interior side by a temporary metallic structure partially on the main surface and partially in the hole;
wherein the method comprises forming the hole by drilling;
wherein the method comprises processing the first hole portion and the second hole portion by electroless plating of metal in both the first hole portion and the second hole portion, followed by electroplating of metal in the first hole portion but not in the second hole portion, and followed by removing the electroless plated metal in the second hole portion.
19. A method, comprising:
providing a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; and
a hole in the stack having a first hole portion covered with metal and having a second hole portion not covered with metal;
wherein the second hole portion is defined by an anti-plating dielectric structure and an electroless plateable separation barrier, the second hole portion extending from the anti-plating dielectric structure to a main surface of the stack; and
using the component carrier for conducting a signal having a frequency greater than or equal to 100 MHz.
20. The method according to claim 19 , comprising at least one of the following features:
wherein the component carrier is used for wireless communication;
wherein the component carrier is used for high-frequency applications with frequencies in a range from 100 MHz to 300 GHz.