Dual vector arithmetic logic unit
A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.
1. A system comprising:
a cache to store a set of operands transferred from a set of vector general purpose register (VGPR) banks; and
an execution unit comprising a first arithmetic logic unit (ALU) pipeline and a second ALU pipeline to selectively execute either a single instruction at each of the first ALU pipeline and the second ALU pipeline using the first set of operands in an execution cycle or a pair of independent instructions at respective ALU pipelines of the first ALU pipeline and the second ALU pipeline using the first set of operands in the execution cycle.
2. The system of claim 1 , further comprising:
the set of VGPR banks to transfer operands to the cache.
3. The system of claim 2 , wherein the set of VGPR banks receives the operands from local data share return data, texture return data, VGPR initialization inputs, or any combination thereof.
4. The system of claim 1 , further comprising:
a buffer to store results of the single instruction or the pair of independent instructions; and
a controller to cause some or all of the results to be sent to the cache, the set of VGPR banks, or both.
5. The system of claim 1 , wherein the cache is configured to store received results as operands for a future instruction.
6. The system of claim 1 , wherein a number of operands in the set of operands equals a number of ALUs in the first ALU pipeline plus a number of ALUs in the second ALU pipeline.
7. The system of claim 6 , wherein the set of operands further includes an indication that the number of operands in the set of operands equals the number of ALUs in the first ALU pipeline plus the number of ALUs in the second ALU pipeline.
8. The system of claim 1 , wherein the set of operands further includes indications of ALUs that are to receive respective operands of the set of operands.
9. An apparatus, comprising:
a set of vector general purpose register (VGPR) banks to store a set of vectors;
a cache to store the set of vectors transferred from the set of VGPR banks; and
an execution unit comprising a first arithmetic logic unit (ALU) pipeline and a second ALU pipeline to selectively execute either a single instruction or a dual instruction on the set of vectors in an execution cycle both at the first ALU pipeline and at the second ALU pipeline.
10. The apparatus of claim 9 , further comprising:
an instruction buffer to send, to the execution unit, a vector instruction to perform operations on vectors from the cache, wherein the vector instruction is either the single instruction or the dual instruction.
11. The apparatus of claim 9 , further comprising:
a buffer to store results of the single instruction or the dual instruction; and
a controller to cause the results of the single instruction or the dual instruction to be sent to the cache, the set of VGPR banks, or both.
12. The apparatus of claim 9 , wherein a number of work items in the set of vectors equals a number of ALUs in the first ALU pipeline.
13. The apparatus of claim 12 , wherein a number of ALUs in the second ALU pipeline equals the number of ALUs in the first ALU pipeline.
14. The apparatus of claim 12 , wherein the set of vectors further includes an indication that the number of vectors in the set of operands equals the number of ALUs in the first ALU pipeline.
15. The apparatus of claim 9 , wherein the set of vectors further includes indications of ALUs that are to receive respective vectors of the set of vectors.
16. A method, comprising:
transferring a set of warps from a set of vector general purpose register (VGPR) banks to an execution unit via a cache; and
selectively executing, at the execution unit, either a single instruction or a dual instruction on the set of warps in an execution cycle both at a first ALU pipeline and at a second ALU pipeline.
17. The method of claim 16 , wherein:
a number of work items in the set of warps equals a number of ALUs of the first ALU pipeline plus a number of ALUs of the second ALU pipeline; and
selectively executing comprises executing the single instruction both at the first ALU pipeline and at the second ALU pipeline in the execution cycle.
18. The method of claim 16 , wherein:
a number of work items in the set of warps equals a number of ALUs of the first ALU pipeline; and
selectively executing comprises executing the dual instruction at respective ALU pipelines of the first ALU pipeline and the second ALU pipeline.
19. The method of claim 16 , further comprising:
storing results of the single instruction or the dual instruction at a buffer.
20. The method of claim 19 , further comprising:
transferring the results from the buffer to the cache or the set of VGPR banks in response to a determination that the results are to be used in execution of a future instruction.