IP Library › Granted Patent US 12,299,422
Granted Patent B2
US 12,299,422 · App. 18/108,556 · Granted May 13, 2025

Quantum computer using switchable couplings between logical qubits

Inventor: Daniel Litinski (Palo Alto, CA)
Assignee: Psiquantum, Corp.
G06F8/41G06F13/4022G06N10/20G06N10/40G06N10/70H04B10/70H04Q11/0005H04Q2011/0043
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Quick Facts
Patent No.
US 12,299,422
App. No.
18/108,556
Granted
May 13, 2025
Kind
B2
Abstract

A fault-tolerant quantum computer using topological codes such as surface codes can have an architecture that reduces the amount of idle volume generated. The architecture can include qubit modules that generate surface code patches for different qubits and a network of interconnections between different qubit modules. The interconnections can include “port” connections that selectably enable coupling of boundaries of surface code patches generated in different qubit modules and/or “quickswap” connections that selectably enable transferring the state of a surface code patch from one qubit module to another. Port and/or quickswap connections can be made between a subset of qubit modules. For instance port connections can connect a given qubit module to other qubit modules within a fixed range. Quickswap connections can provide a log-tree network of direct connections between qubit modules.

Claims (99)

1. A circuit comprising:

a resource state interconnect having a plurality of output paths to output a resource state during each of a plurality of operating cycles, wherein each resource state is a quantum system of multiple entangled physical qubits, wherein different physical qubits of the resource state are output on a different ones of the output paths;

a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits being configured to receive two input physical qubits and to selectably perform either a projective entangling measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby producing measurement outcome data;

a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input path,

wherein, for each routing switch, the plurality of output routing paths includes a first local path, wherein the first local paths of different ones of the routing switches introduce different delays,

wherein, for a first one of the routing switches, the plurality of output routing paths further includes a plurality of internal quickswap routing paths, and

wherein, for a second one of the routing switches, the plurality of output routing paths further includes a plurality of quickswap transfer paths that exit the circuit; and

a plurality of external quickswap routing paths that receive physical qubits from a plurality of external circuits,

wherein the plurality of reconfigurable fusion circuits includes:

a plurality of local fusion circuits, wherein each local fusion circuit is coupled to respective first local routing paths of two of the routing switches; and

a plurality of quickswap fusion circuits, wherein each quickswap fusion circuit has a first input coupled to one of the internal quickswap routing paths of the first one of the routing switches and a second input coupled to one of the of the external quickswap routing paths.

2. The circuit of claim 1 wherein the circuit is one of a plurality of instances of the circuit and wherein, for each routing switch, the quickswap transfer paths are coupled to the external quickswap routing paths of other instances of the circuit.

3. The circuit of claim 2 wherein each of the routing switches is associated with a different surface of a topological code patch for a fault-tolerant logical qubit, and wherein the quickswap fusion circuits operate on physical qubits from an upper surface of one topological code patch and physical qubits from a lower surface of another topological code patch.

4. A circuit comprising:

a resource state interconnect having a plurality of output paths to output a resource state during each of a plurality of operating cycles, wherein each resource state is a quantum system of multiple entangled physical qubits, wherein different physical qubits of the resource state are output on a different ones of the output paths;

a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits being configured to receive two input physical qubits and to selectably perform either a projective entangling measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby producing measurement outcome data;

a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input path, wherein, for each routing switch, the plurality of output routing paths includes:

a first local path, wherein the first local paths of different ones of the routing switches introduce different delays;

a plurality of internal port routing paths; and

a plurality of port transfer paths that exit the circuit; and

a plurality of external port routing paths to receive physical qubits from a plurality of external circuits,

wherein the plurality of reconfigurable fusion circuits includes:

a plurality of local fusion circuits, wherein each local fusion circuit is coupled to respective first local routing paths of two of the routing switches; and

a plurality of port fusion circuits, wherein each port fusion circuit has a first input coupled to one of the internal port routing paths of one of the routing switches and a second input coupled to one of the of the external port routing paths, and

wherein, for a first one of the routing switches, the plurality of output routing paths further includes a plurality of internal quickswap routing paths, and

wherein, for a second one of the routing switches, the plurality of output routing paths further includes a plurality of quickswap transfer paths that exit the circuit; and

a plurality of external quickswap routing paths that receive physical qubits from a plurality of external circuits,

wherein the plurality of reconfigurable fusion circuits includes:

a plurality of local fusion circuits, wherein each local fusion circuit is coupled to respective first local routing paths of two of the routing switches; and

a plurality of quickswap fusion circuits, wherein each quickswap fusion circuit has a first input coupled to one of the internal quickswap routing paths of the first one of the routing switches and a second input coupled to one of the of the external quickswap routing paths.

5. The circuit of claim 4 wherein the circuit is one of a plurality of instances of the circuit and wherein, for each routing switch, the port transfer paths are coupled to the external port routing paths of other instances of the circuit.

6. The circuit of claim 5 wherein each of the routing switches is associated with a different surface of a topological code patch for a fault-tolerant logical qubit, and wherein the port fusion circuits operate on physical qubits from like surfaces of different topological code patches.

7. The circuit of claim 4 wherein the plurality of local fusion circuits includes a first local fusion circuit, a second local fusion circuit, and a third local fusion circuit and wherein:

one of the first local routing paths coupled to the first local fusion circuit introduces a delay of one operating cycle relative to the other of the first local routing paths coupled to the first local fusion circuit;

one of the first local routing paths coupled to the second local fusion circuit introduces a delay of a number d of operating cycles relative to the other of the first local routing paths coupled to the second local fusion circuit, wherein the number dis a code distance greater than 1; and

one of the first local routing paths coupled to the third local fusion circuit introduces a delay of a number d 2 of operating cycles relative to the other of the first local routing paths coupled to the third local fusion circuit.

8. The circuit of claim 7 wherein:

the first local fusion circuit is coupled to the respective first local routing paths of a first routing switch and a second routing switch;

the first local routing path of the first routing switch introduces the delay of one operating cycle;

the plurality of output routing paths of each of the first routing switch and the second routing switch further includes a third local routing path, wherein the third local routing path of the first routing switch introduces a delay of two operating cycles relative to the third local routing path of the second routing switch; and

the plurality of local fusion circuits further includes a fourth local fusion circuit coupled to the third local routing paths of the first routing switch and the second routing switch.

9. The circuit of claim 7 wherein:

the third local fusion circuit is coupled to the respective first local routing paths of a first routing switch and a second routing switch;

the first local routing path of the first routing switch introduces the delay of d 2 operating cycles; and

the plurality of quickswap transfer paths exit the circuit after a delay of d 2 operating cycles.

10. The circuit of claim 4 wherein each of the plurality of reconfigurable fusion circuits is configured such that the projective entangling measurement operation includes a destructive measurement on both of the input qubits.

11. The circuit of claim 4 wherein each of the reconfigurable fusion circuits is configured such that the projective entangling measurement is a type II fusion operation that provides a joint XX measurement outcome and a joint ZZ measurement outcome.

12. The circuit of claim 4 wherein each of the reconfigurable fusion circuits is configured such that the plurality of single-qubit measurements includes at least one of:

a Pauli X measurement;

a Pauli Y measurement;

a Pauli Z measurement; or

a phase rotation of e −iπ/8 followed by a Pauli Z measurement.

13. The circuit of claim 4 further comprising:

classical control logic coupled to the plurality of reconfigurable fusion circuits and to the plurality of routing switches, the classical control logic being configured to select an output routing path for the each of the plurality of routing switches and an operation for each of the plurality of reconfigurable fusion circuits.

14. The circuit of claim 4 wherein the physical qubits of the resource state are photonic qubits.

15. The circuit of claim 14 wherein the resource state interconnect includes a plurality of waveguides coupled between an external source of resource states and the output paths of the resource state interconnect.

16. A system comprising:

a network of interleaving modules, each interleaving module including:

a resource state interconnect having a plurality of output paths to output a resource state during each of a plurality of operating cycles, wherein each resource state is a quantum system of multiple entangled physical qubits, wherein different physical qubits of the resource state are output on a different ones of the output paths;

a plurality of reconfigurable fusion circuits, each of the plurality of reconfigurable fusion circuits being configured to receive two input physical qubits and to selectably perform either a projective entangling measurement between the two input physical qubits or one of a plurality of single-qubit measurements on each of the two input physical qubits, thereby producing measurement outcome data;

a plurality of routing switches, each routing switch having an input path coupled to a respective one of the output paths of the resource state interconnect and a plurality of output routing paths selectably coupled to the input path, wherein, for each routing switch, the plurality of output routing paths includes:

a first local path, wherein the first local paths of different ones of the routing switches introduce different delays;

a plurality of internal port routing paths; and

a plurality of port transfer paths that exit the interleaving module; and

a plurality of external port routing paths to receive physical qubits from a plurality of other interleaving modules in the network,

wherein the plurality of reconfigurable fusion circuits includes:

a plurality of local fusion circuits, wherein each local fusion circuit is coupled to respective first local routing paths of two of the routing switches; and

a plurality of port fusion circuits, wherein each port fusion circuit has a first input coupled to one of the internal port routing paths of one of the routing switches and a second input coupled to one of the of the external port routing paths, and

wherein, for a first one of the routing switches, the plurality of output routing paths further includes a plurality of internal quickswap routing paths, and

wherein, for a second one of the routing switches, the plurality of output routing paths further includes a plurality of quickswap transfer paths that exit the circuit; and

a plurality of external quickswap routing paths that receive physical qubits from a plurality of external circuits,

wherein the plurality of reconfigurable fusion circuits includes:

a plurality of local fusion circuits, wherein each local fusion circuit is coupled to respective first local routing paths of two of the routing switches; and

a plurality of quickswap fusion circuits, wherein each quickswap fusion circuit has a first input coupled to one of the internal quickswap routing paths of the first one of the routing switches and a second input coupled to one of the of the external quickswap routing paths.

17. The system of claim 16 wherein, in each interleaving module, each of the routing switches is associated with a different surface of a topological code patch for a fault-tolerant logical qubit, and wherein the port fusion circuits operate on physical qubits from like surfaces of different topological code patches.

18. The system of claim 16 wherein, in each interleaving module, the plurality of local fusion circuits includes a first local fusion circuit, a second local fusion circuit, and a third local fusion circuit and wherein:

one of the first local routing paths coupled to the first local fusion circuit introduces a delay of one operating cycle relative to the other of the first local routing paths coupled to the first local fusion circuit;

one of the first local routing paths coupled to the second local fusion circuit introduces a delay of a number d of operating cycles relative to the other of the first local routing paths coupled to the second local fusion circuit, wherein the number dis a code distance greater than 1; and

one of the first local routing paths coupled to the third local fusion circuit introduces a delay of a number d 2 of operating cycles relative to the other of the first local routing paths coupled to the third local fusion circuit.

19. The system of claim 18 wherein, in each interleaving module:

the first local fusion circuit is coupled to the respective first local routing paths of a first routing switch and a second routing switch;

the first local routing path of the first routing switch introduces the delay of one operating cycle;

the plurality of output routing paths of each of the first routing switch and the second routing switch further includes a third local routing path, wherein the third local routing path of the first routing switch introduces a delay of two operating cycles relative to the third local routing path of the second routing switch; and

the plurality of local fusion circuits further includes a fourth local fusion circuit coupled to the third local routing paths of the first routing switch and the second routing switch.

20. The system of claim 18 wherein, in each interleaving module:

the third local fusion circuit is coupled to the respective first local routing paths of a first routing switch and a second routing switch;

the first local routing path of the first routing switch introduces the delay of d 2 operating cycles; and

the plurality of quickswap transfer paths exit the circuit after a delay of d 2 operating cycles.

21. The system of claim 16 wherein, in each interleaving module:

each of the reconfigurable fusion circuits is configured such that the projective entangling measurement is a type II fusion operation that provides a joint XX measurement outcome and a joint ZZ measurement outcome; and

each of the reconfigurable fusion circuits is configured such that the plurality of single-qubit measurements includes at least one of:

a Pauli X measurement;

a Pauli Y measurement; a Pauli Z measurement; and

a phase rotation of e −iπ/8 followed by a Pauli Z measurement.

22. The system of claim 16 further comprising:

classical control logic coupled to the plurality of reconfigurable fusion circuits and to the plurality of routing switches in the interleaving modules, the classical control logic being configured to select an output routing path for the each of the plurality of routing switches and an operation for each of the plurality of reconfigurable fusion circuits.

23. The system of claim 22 wherein the classical control logic is further configured to select the output routing path for the each of the plurality of routing switches and the operation for each of the plurality of reconfigurable fusion circuits based at least in part on a logical block network representing a quantum computation to be executed.

24. The system of claim 16 wherein the physical qubits of the resource state are photonic qubits.

25. The system of claim 16 wherein the resource state interconnect includes a plurality of waveguides coupled between an external source of resource states and the output paths of the resource state interconnect.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2023
From: LITINSKI, DANIEL
To: PSIQUANTUM, CORP.
Reel/Frame 063494/0059 →
Continuity (3)
Provisional Application 63427083 · Nov 21, 2022
Provisional Application 63308879 · Feb 10, 2022
Related Publication 20240171889A1 · May 23, 2024
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