IP Library › Granted Patent US 12,299,538
Granted Patent B2
US 12,299,538 · App. 17/257,895 · Granted May 13, 2025

Preparing superpositions of computational basis states on a quantum computer

Inventors: Zhang Jiang (El Segundo, CA); Ryan Babbush (Venice, CA)
Assignee: Google LLC
G06N10/60G06F9/30101G06N10/20
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Quick Facts
Patent No.
US 12,299,538
App. No.
17/257,895
Granted
May 13, 2025
Kind
B2
Abstract

Methods, systems and apparatus for preparing arbitrary superposition quantum states of a quantum register on a quantum computer, the quantum state comprising a superposition of L computational basis states. In one aspect, a register of log L qubits is prepared in a weighted sum of register basis states, where each register basis state indexes a corresponding quantum state computational basis state, and the amplitude of each register basis state in the weighted sum of register basis states is equal to the amplitude of the corresponding computational basis state in the superposition of L computational basis states. A unitary transformation that maps the register basis states to the corresponding L computational basis states is then implemented, including, for each index 1 to L, controlling, by the register of log L qubits, transformation of the quantum system register state for the index to the corresponding computational basis state for the index.

Claims (74)

1. A method for preparing a quantum state of a quantum system register on a quantum computer, wherein the quantum state comprises a superposition of L computational basis states, the method comprising:

preparing a register of log L qubits in an initial state, the initial state comprising a weighted sum of register basis states, wherein:

each register basis state indexes a corresponding quantum state computational basis state, and

an amplitude of each register basis state in the weighted sum of register basis states is equal to the amplitude of the corresponding computational basis state in the superposition of L computational basis states; and

preparing the quantum state by implementing a unitary transformation that maps the register basis states to the corresponding L computational basis states, comprising, for each index 1 to L;

controlling, by the register of log L qubits, transformation of the quantum system register state for the index to the corresponding computational basis state for the index, comprising:

applying a unitary operator for the index to the quantum system register state controlled by a state of a unary register, wherein the state of the unary register is determined by the register of log L qubits, to read the computational basis state corresponding to the index to the quantum system register,

erasing the state of the register of log L qubits using a unitary operator controlled by the unary register to put the register of log L qubits in a zero state; and

un-computing the unary register.

2. The method of claim 1 , wherein applying a unitary operator for the index to the quantum system register state controlled by a state of a unary register, wherein the state of the unary register is determined by the register of log L qubits, to read the computational basis state corresponding to the index to the quantum system register comprises implementing a unary iteration quantum circuit.

3. The method of claim 1 , further comprising providing the register of log L qubits for use in further computations.

4. The method of claim 1 , wherein applying the unitary operator for the index to the quantum system register state controlled by the state of the unary register that is determined by the register of log L qubits comprises controlling applications of products of Pauli-X quantum logic gates.

5. The method of claim 1 , wherein implementing a unitary transformation that maps the register basis states to the corresponding L computational basis states comprises applying select unitary methods.

6. The method of claim 1 , wherein preparing the register of log L qubits in the initial state comprises applying quantum circuit synthesis techniques.

7. The method of claim 1 , wherein the superposition of L computational basis states is determined using an adaptive sampling configuration interaction method.

8. The method of claim 1 , further comprising providing the quantum state for use in a quantum phase estimation algorithm.

9. The method of claim 1 , further comprising:

performing a quantum simulation using the prepared quantum state as an initial state of the quantum simulation.

10. The method of claim 1 , wherein the quantum computer comprises a circuit model quantum computer.

11. An apparatus comprising:

quantum hardware; and

one or more classical processors;

wherein the apparatus is configured to perform operations for preparing a quantum state of a quantum system register on a quantum computer, wherein the quantum state comprises a superposition of L computational basis states, the operations comprising:

preparing a register of log L qubits in an initial state, the initial state comprising a weighted sum of register basis states, wherein:

each register basis state indexes a corresponding quantum state computational basis state, and

an amplitude of each register basis state in the weighted sum of register basis states is equal to the amplitude of the corresponding computational basis state in the superposition of L computational basis states; and

preparing the quantum state by implementing a unitary transformation that maps the register basis states to the corresponding L computational basis states, comprising, for each index 1 to L;

controlling, by the register of log L qubits, transformation of the quantum system register state for the index to the corresponding computational basis state for the index, comprising:

applying a unitary operator for the index to the quantum system register state controlled by a state of a unary register, wherein the state of the unary register is determined by the register of log L qubits, to read the computational basis state corresponding to the index to the quantum system register,

erasing the state of the register of log L qubits using a unitary operator controlled by the unary register to put the register of log L qubits in a zero state; and

un-computing the unary register.

12. The apparatus of claim 11 , wherein the quantum hardware comprises:

a quantum circuit comprising:

a quantum system register comprising multiple target qubits;

an index register comprising log L index qubits;

a control register comprising multiple control qubits;

one or more control devices configured to operate the quantum circuit.

13. A method for preparing a target quantum state of a quantum system register on a quantum computer, wherein the target quantum state comprises a superposition of L computational basis states, the method comprising, sequentially for each index l=1 to l=L:

preparing the quantum system register and a unary register in a quantum state, wherein:

the state of the quantum system register is entangled with the unary register,

at an initial time step the state of the quantum system register equals the target quantum state up to the first (l−1) computational basis states if the state of the unary register is |0 , and

the state of the quantum system register equals a l-th computational basis state if the unary register is in state |1 ;

selecting a qubit from the quantum system register whose value is different in the l-th computational basis state and a l+1-th computational basis state;

applying a rotation to the selected qubit, wherein the rotation is controlled by the state of a unary register;

erasing the unary register value for the l-th computational basis state; and

implementing a NOT logic gate on the remaining qubits in the quantum system register whose values are different in the l-th computational basis state and the l+1-th computational basis state, wherein implementation of the NOT logic gate is controlled by the state of the unary register.

14. The method of claim 13 , wherein preparing the quantum system register and a see tiff unary register in a quantum state comprises preparing the quantum system register and unary for register in a quantum state |ψ l −β l |D l |1 +Σ l′=1 l−1 α l′ |D l′ |0 , wherein l represents the index, |D l represents the l-th computational basis state, α represents a computational basis state amplitude, and |β l |=√{square root over (1−Σ l′=1 l−1 |α l′ | 2 )}.

15. The method of claim 13 , further comprising ordering the computational basis states such that Hamming distances between neighboring computational basis states are reduced.

16. The method of claim 13 , wherein applying a rotation to the selected qubit comprises applying a Pauli X gate to the selected qubit.

17. The method of claim 13 , wherein selecting a qubit from the quantum system register whose value is different the l-th computational basis state and the l+l-th computational basis state comprises selecting a qubit from the quantum system whose occupation numbers d l,k and d l+1,k are different.

18. The method of claim 13 , wherein an amplitude of the l-th basis state is derived from normalization.

19. The method of claim 14 , wherein |β l |, is derived from normalization.

20. The method of claim 13 , wherein the superposition of L computational basis states is determined using an adaptive sampling configuration interaction method.

21. The method of claim 13 , further comprising providing the target quantum state for use in a quantum phase estimation algorithm.

22. The method of claim 13 , further comprising:

initializing a quantum simulation using the prepared target quantum state; and

performing a the quantum simulation.

23. An apparatus comprising:

quantum hardware; and

one or more classical processors;

wherein the apparatus is configured to perform operations for preparing a target quantum state of a quantum system register on a quantum computer, wherein the target quantum state comprises a superposition of L computational basis states, the operations comprising, sequentially for each index l=1 to l=L:

preparing the quantum system register and a unary register in a quantum state, wherein:

the state of the quantum system register is entangled with the unary register,

at an initial time step the state of the quantum system register equals the target quantum state up to the first (l−1) computational basis states if the state of the unary register is |0 , and

the state of the quantum system register equals a l-th computational basis state if the unary register is in state |l ;

selecting a qubit from the quantum system register whose value is different in the l-th computational basis state and the l+1-th computational basis state;

applying a rotation to the selected qubit, wherein the rotation is controlled by the state of a unary register;

erasing the unary register value for the 1-th computational basis state; and

implementing a NOT logic gate on the remaining qubits in the quantum system register whose values are different in the l-th computational basis state and the l+1-th computational basis state, wherein implementation of the NOT logic gate is controlled by the state of the unary register.

24. The apparatus of claim 23 , wherein the quantum hardware comprises:

a quantum circuit comprising:

a quantum system register comprising multiple target qubits;

a unary register comprising multiple control qubits; and

one or more control devices configured to operate the quantum.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2021
From: JIANG, ZHANG; BABBUSH, RYAN
To: GOOGLE LLC
Reel/Frame 055109/0416 →
Continuity (2)
Provisional Application 62694850 · Jul 6, 2018
Related Publication 20210271477A1 · Sep 2, 2021
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