Method for pulse-based convolution for near-sensor processing
Disclosed herein is a low-cost, high-performance, and energy-efficient near-sensor convolution engine based on pulsed unary processing. The disclosed engine removes the necessity of using costly analog-to-digital converters. Synthesis results show that the proposed pulse-based design significantly improves the hardware cost and energy consumption compared to the conventional fixed-point binary and also to the stochastic computing-based designs.
1. An N×N bipolar near-sensor convolutional engine comprising:
two or more pulse width modulation (PWM) signal generators, comprising two or more inputs;
two or more AND gates comprising configuration to perform multiplications in a pulsed unary domain;
wherein the two or more AND gates each comprise an output; and
wherein the outputs of each AND are connected to a time-to-voltage converter;
wherein the time-to-voltage converter comprises an integrator comprising functionality to integrate outputs of the AND gates;
wherein the each PWM signal generator of the two or more PWM signal generators comprises functionality to convert an analog input data to a PWM signal with a corresponding duty cycle;
wherein the time-to-voltage converter comprises functionality to accumulate and integrate one or more output signals over time; and
wherein the time-to-voltage converter comprises functionality to generate an analog voltage output.
2. The engine of claim 1 , wherein the integrator comprising functionality to integrate outputs of the AND gates in an analog domain.
3. The engine of claim 1 , wherein the time-to-voltage converter comprises an integrator comprising functionality to integrate outputs of the AND gates in an analog domain; and wherein the integrator converts to the outputs' corresponding currents.
4. The engine of claim 1 , wherein the time-to-voltage converter comprises an integrator comprising functionality to integrate outputs of the AND gates in an analog domain; and wherein the integrator converts to the outputs' corresponding currents; and wherein a capacitor integrates the converted inputs over time.
5. The engine of claim 1 , wherein the time-to-voltage converter comprises an integrator comprising functionality to integrate outputs of the AND gates in an analog domain; and wherein the integrator converts to the outputs' corresponding currents; and wherein the integrator uses an identical current source for all inputs.
6. The engine of claim 1 , wherein the time-to-voltage converter comprises an integrator comprising functionality to integrate outputs of the AND gates in an analog domain; and wherein the integrator converts to the outputs' corresponding currents; wherein a capacitor integrates the converted inputs over time; and
wherein each input applies a current into the capacitor measured by a length of the input signal's high parts.
7. The engine of claim 1 , further comprising two PMOS transistors comprising functionality to implement a current source.
8. The engine of claim 1 , further comprising two PMOS transistors and at least one capacitor.
9. The engine of claim 1 , further comprising two PMOS transistors and at least one capacitor, wherein the PMOS transistors comprising functionality to route a current source to the capacitor.
10. The engine of claim 1 , further comprising two PMOS transistors and at least one capacitor, wherein in a high phase of an output signal, one PMOS transistor sinks applied current into the capacitor.
11. The engine of claim 1 , further comprising two PMOS transistors and at least one capacitor, wherein in a low phase of an output signal, one PMOS transistor sinks applied current into ground.
12. A method for performing pulse-based convolution in a neural network, comprising:
a. Providing an N×N bipolar near-sensor convolutional engine comprising:
two or more pulse width modulation (PWM) signal generators;
two or more AND gates comprising configuration to perform multiplications in a pulsed unary domain; and
a time-to-voltage converter;
b. the each PWM signal generator of the two or more PWM signal generators comprises converts an analog input data to a PWM signal with a corresponding duty signal;
c. time-to-voltage converter that accumulates and integrates one or more output signals over time; and
d. time-to-voltage converter generates an analog voltage output;
e. wherein the time-to-voltage converter comprises an integrator, which integrates the outputs of the AND gates in an analog domain;
f. the integrator converts the one or more output signals to the output signals' corresponding currents and integrates said signals over time in a capacitor;
g. providing two PMOS transistors, which route a current source to a capacitor, wherein when the output signal is in a high phase, one PMOS transistor sinks the current into the capacitor; and
wherein when the output signal is in a low phase, one PMOS transistor sinks the current into ground.
13. The method of claim 12 , wherein the input pulse signals comprise two inharmonic frequencies.
14. The method of claim 12 , wherein the input data is converted to pulse signals by two or more pulse width modulation (PWM) signal generators.
15. The method of claim 12 , wherein the input pulse signals comprise two inharmonic frequencies; and wherein the inharmonic frequencies can be adjusted according to needed accuracy.
16. The method of claim 12 , wherein values of the positive weights and negative weights are determined and fixed in an inference step in the neural network.
17. The method of claim 12 , wherein the integrator uses an identical size current source for all inputs.