Signal skew in source-synchronous system
A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a plurality of data signals to the memory module, wherein a first subset of the plurality of data signals comprises a first nibble and is phase aligned with a first strobe signal of the plurality of strobe signals, and wherein a second subset of the plurality of data signals comprises a second nibble and is phase aligned with a second strobe signal of the plurality of strobe signals.
1. A memory module comprising:
one or more memory devices; and
a command buffer coupled to the one or more memory devices, the command buffer comprising:
a clock receiver circuit configured to receive an external clock signal from a memory controller, the clock receiver circuit to generate a first internal clock signal from the external clock signal;
a plurality of receiver circuits configured to receive a plurality of command/address signals from the memory controller, the plurality of command/address signals to convey a memory access command and an address;
a clock delay circuit configured generate a second internal clock signal from the first internal clock signal, wherein the second internal clock signal is delayed by a first offset amount with respect to the first internal clock signal; and
a sampling circuit configured to sample a first subset of the plurality of command/address signals according to the first internal clock signal and to sample a second subset of the plurality of command signals according to the second internal clock signal.
2. The memory module of claim 1 , wherein the plurality of receiver circuits are further configured to:
calibrate the first offset amount during a calibration operation, wherein the first offset amount is based on a first amount of interference attributable to transitions in the second subset of the plurality of command/address signals propagating on first signal lines.
3. The memory module of claim 1 , wherein to generate the second internal clock signal from the first internal clock signal, the command buffer is configured to apply the first internal clock signal to the clock delay circuit, and wherein an output of the clock delay circuit comprises the second internal clock signal.
4. The memory module of claim 1 , wherein the clock delay circuit is further configured to:
generate a third internal clock signal from the second internal clock signal, wherein the third internal clock signal is delayed by a second offset amount with respect to the second internal clock signal.
5. The memory module of claim 4 , wherein the sampling circuit is further configured to:
sample a third subset of the plurality of command signals according to the third internal clock signal.
6. The memory module of claim 1 , wherein the one or more memory devices comprise dynamic random access memory (DRAM) devices.
7. The memory module of claim 1 , wherein the memory module comprises a dual-in line memory module (DIMM).
8. A method of operation of a memory module, the method comprising:
receiving, at a clock receiver circuit, an external clock signal from a memory controller;
generating, by the clock receiver circuit, a first internal clock signal from the external clock signal;
receiving, at a plurality of receiver circuits, a plurality of command/address signals from the memory controller, the plurality of command/address signals to convey a memory access command and an address;
generating, by a clock delay circuit, a second internal clock signal from the first internal clock signal, wherein the second internal clock signal is delayed by a first offset amount with respect to the first internal clock signal;
sampling, by a sampling circuit, a first subset of the plurality of command/address signals according to the first internal clock signal; and
sampling, by the sampling circuit, a second subset of the plurality of command signals according to the second internal clock signal.
9. The method of claim 8 , further comprising:
calibrating, by the plurality of receiver circuits, the first offset amount during a calibration operation, wherein the first offset amount is based on a first amount of interference attributable to transitions in the second subset of the plurality of command/address signals propagating on first signal lines.
10. The method of claim 8 , wherein generating the second internal clock signal from the first internal clock signal comprises applying the first internal clock signal to the clock delay circuit, and wherein an output of the clock delay circuit comprises the second internal clock signal.
11. The method of claim 8 , further comprising:
generating, by the clock delay circuit, a third internal clock signal from the second internal clock signal, wherein the third internal clock signal is delayed by a second offset amount with respect to the second internal clock signal.
12. The method of claim 11 , further comprising:
sampling, by the sampling circuit, a third subset of the plurality of command signals according to the third internal clock signal.
13. The method of claim 8 , wherein the memory module comprises a dual-in line memory module (DIMM).
14. An command buffer comprising:
a clock receiver circuit configured to receive an external clock signal from a memory controller, the clock receiver circuit to generate a first internal clock signal from the external clock signal;
a plurality of receiver circuits configured to receive a plurality of command/address signals from the memory controller, the plurality of command/address signals to convey a memory access command and an address;
a clock delay circuit configured generate a second internal clock signal from the first internal clock signal, wherein the second internal clock signal is delayed by a first offset amount with respect to the first internal clock signal; and
a sampling circuit configured to sample a first subset of the plurality of command/address signals according to the first internal clock signal and to sample a second subset of the plurality of command signals according to the second internal clock signal.
15. The command buffer of claim 14 , wherein the plurality of receiver circuits are further configured to:
calibrate the first offset amount during a calibration operation, wherein the first offset amount is based on a first amount of interference attributable to transitions in the second subset of the plurality of command/address signals propagating on first signal lines.
16. The command buffer of claim 14 , wherein to generate the second internal clock signal from the first internal clock signal, the command buffer is configured to apply the first internal clock signal to the clock delay circuit, and wherein an output of the clock delay circuit comprises the second internal clock signal.
17. The command buffer of claim 14 , wherein the clock delay circuit is further configured to:
generate a third internal clock signal from the second internal clock signal, wherein the third internal clock signal is delayed by a second offset amount with respect to the second internal clock signal.
18. The command buffer of claim 17 , wherein the sampling circuit is further configured to:
sample a third subset of the plurality of command signals according to the third internal clock signal.
19. The command buffer of claim 14 , wherein the command buffer is coupled to one or more memory devices.
20. The command buffer of claim 14 , wherein the command buffer is disposed within a dual-in line memory module (DIMM).