Semiconductor device and method of manufacturing thereof
In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.
1. A semiconductor device, comprising:
a first dielectric layer;
a redistribution layer formed in the first dielectric layer, including a first liner conductive layer, a main conductive layer disposed over the first liner conductive layer, and a cover conductive layer; and
a second dielectric layer disposed over the cover conductive layer and the first dielectric layer,
wherein the main conductive layer is fully wrapped around by the cover conductive layer and the first liner conductive layer.
2. The semiconductor device of claim 1 , wherein the first liner conductive layer and the cover layer are made of a same metal material.
3. The semiconductor device of claim 2 , wherein the same metal material is Co.
4. The semiconductor device of claim 1 , further comprising:
a second liner conductive layer below the first liner conductive layer; and
a third liner conductive layer over the first liner conductive layer,
wherein first, second and third liner conductive layers are made of different materials from each other.
5. The semiconductor device of claim 4 , wherein the first liner conductive layer is made of Co.
6. The semiconductor device of claim 5 , wherein the second liner conductive layer includes one or more of TaN, Ta, Ti, TiN or TiW.
7. The semiconductor device of claim 6 , wherein the third liner conductive layer includes Cu or a Cu alloy.
8. The semiconductor device of claim 7 , wherein the main conductive layer includes Cu or a Cu alloy.
9. A semiconductor device, comprising:
a pad electrode formed in or on a first dielectric layer;
a second dielectric layer disposed over the first dielectric layer;
a redistribution layer having a via portion passing through the second dielectric layer and connected to the pad electrode and a wire portion disposed on an upper surface of the second dielectric layer;
a third dielectric layer disposed over the redistribution layer; and
a bump electrode connected to the redistribution layer through an opening formed in the third dielectric layer, wherein:
the redistribution layer includes a liner conductive layer, a main conductive layer disposed over the liner conductive layer, and a cover conductive layer, and
the main conductive layer is fully sealed by the cover conductive layer and the liner conductive layer.
10. The semiconductor device of claim 9 , wherein the main conductive layer is not in contact with the second dielectric layer and the third dielectric layer.
11. The semiconductor device of claim 9 , wherein a part of the cover conductive layer is disposed between the bump electrode and the main conductive layer.
12. The semiconductor device of claim 9 , wherein a part of the main conductive layer is in contact with the bump electrode.
13. The semiconductor device of claim 9 , wherein a center of the pad electrode is laterally shifted from a center of the bump electrode.
14. The semiconductor device of claim 9 , wherein:
the liner conductive layer and the cover conductive layer are made of Co, and
the main conductive layer is made of Cu or a Cu alloy.
15. The semiconductor device of claim 9 , further comprising a barrier layer below the liner layer.
16. The semiconductor device of claim 15 , wherein the barrier layer includes one or more of TaN, Ta, Ti, TiN or TiW.
17. A semiconductor device, comprising:
a trench disposed in a first dielectric layer, the trench including a shallow wire portion and a deep via portion having a greater depth than the shallow wire portion;
one or more liner conductive layers disposed in the trench;
a main conductive layer disposed over the one or more liner conductive layers in the trench;
a cover conductive layer disposed over the main conductive layer; and
a second dielectric layer disposed over the cover layer and the first dielectric layer
wherein the main conductive layer is fully wrapped around by the cover conductive layer and one of the one or more liner conductive layers.
18. The semiconductor device of claim 17 , wherein the cover conductive layer is not disposed on an upper surface of the first dielectric layer.
19. The semiconductor device of claim 17 , wherein:
the one of the one or more liner conductive layers and the cover layer are made of a same metal material, and
the same metal material is one of Co, V, Ta, Ti, Mo, Ni, Y, Nb, Zr, Ru, Re, Rh, Pd or Ir.
20. The semiconductor device of claim 17 , wherein the main conductive layer is not in contact with the first and second dielectric layers.