Semiconductor package and method of fabricating the same
Provided is a semiconductor package, including a lower semiconductor chip, a plurality of semiconductor chips that are disposed on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip, a plurality of nonconductive layers disposed between the plurality of semiconductor chips, a nonconductive pattern that extends from the nonconductive layers and is disposed on lateral surfaces of at least one of the plurality of semiconductor chips, a first mold layer disposed a top surface of the nonconductive pattern, and a second mold layer disposed a lateral surface of the nonconductive pattern and a lateral surface of the first mold layer, wherein the nonconductive pattern and the first mold layer are disposed between the second mold layer and lateral surfaces of the plurality of semiconductor chips.
1. A semiconductor package, comprising:
a lower semiconductor chip;
a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip;
a plurality of nonconductive layers between the plurality of semiconductor chips;
a nonconductive pattern that extends from the nonconductive layers and is on lateral surfaces of at least one of the plurality of semiconductor chips;
a first mold layer on a top surface of the nonconductive pattern; and
a second mold layer on a lateral surface of the nonconductive pattern and a lateral surface of the first mold layer,
wherein the nonconductive pattern and the first mold layer are between the second mold layer and lateral surfaces of the plurality of semiconductor chips, and
wherein the first mold layer and the second mold layer expose a top surface of an uppermost semiconductor chip among the plurality of semiconductor chips.
2. The semiconductor package of claim 1 , wherein the first mold layer and the second mold layer contact each other while having an interface between the first mold layer and the second mold layer.
3. The semiconductor package of claim 1 , wherein the nonconductive pattern includes a material the same as a material of the nonconductive layers.
4. The semiconductor package of claim 1 , wherein the plurality of semiconductor chips and the nonconductive pattern are on the top surface of the lower semiconductor chip, and
wherein the nonconductive pattern is on a portion of the top surface of the lower semiconductor chip.
5. The semiconductor package of claim 4 , wherein the second mold layer is on at least a portion of a lateral surface of the lower semiconductor chip.
6. The semiconductor package of claim 4 , wherein the second mold layer extends onto a lateral surface of the lower semiconductor chip and is on an entirety of the lateral surface of the lower semiconductor chip.
7. The semiconductor package of claim 4 , wherein the second mold layer extends onto a lateral surface of the lower semiconductor chip and exposes a portion of the lateral surface of the lower semiconductor chip.
8. The semiconductor package of claim 4 , wherein the second mold layer is on the top surface of the lower semiconductor chip and exposes a lateral surface of the lower semiconductor chip.
9. The semiconductor package of claim 1 , wherein the second mold layer has an inner surface and an outer surface that are opposite to each other, and
wherein the inner surface of the second mold layer is in contact with the lateral surface of the nonconductive pattern and with the lateral surface of the first mold layer.
10. The semiconductor package of claim 9 , wherein the second mold layer extends onto a lateral surface of the lower semiconductor chip, and
wherein the inner surface of the second mold layer is in contact with the lateral surface of the lower semiconductor chip.
11. The semiconductor package of claim 9 , wherein the outer surface of the second mold layer is aligned with at least a portion of a lateral surface of the lower semiconductor chip.
12. The semiconductor package of claim 1 , wherein the plurality of semiconductor chips are memory chips, and
wherein the lower semiconductor chip is a logic chip.
13. A semiconductor package, comprising:
a lower semiconductor chip;
a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip;
a plurality of bumps between the plurality of semiconductor chips and connecting the plurality of semiconductor chips to each other;
a plurality of nonconductive layers between the plurality of semiconductor chips, each of the plurality of nonconductive layers being between corresponding ones of the plurality of bumps and between neighboring ones of the plurality of semiconductor chips;
a nonconductive pattern that extends from the nonconductive layers and is on lateral surfaces of at least one of the plurality of semiconductor chips;
a first mold layer on a top surface of the nonconductive pattern; and
a second mold layer on a lateral surface of the nonconductive pattern and a lateral surface of the first mold layer,
wherein the nonconductive pattern and the first mold layer are between the second mold layer and lateral surfaces of the plurality of semiconductor chips,
wherein each of the plurality of semiconductor chips includes a plurality of through electrodes, and
wherein the plurality of semiconductor chips are connected to each other through the plurality of through electrodes and the plurality of bumps, and
wherein the first mold layer and the second mold layer expose a top surface of an uppermost semiconductor chip among the plurality of semiconductor chips.
14. The semiconductor package of claim 13 , wherein the plurality of semiconductor chips and the nonconductive pattern are on the top surface of the lower semiconductor chip, and
wherein the nonconductive pattern is on a portion of the top surface of the lower semiconductor chip.
15. The semiconductor package of claim 14 , wherein the second mold layer is on at least a portion of a lateral surface of the lower semiconductor chip.
16. The semiconductor package of claim 14 , wherein the second mold layer is on the top surface of the lower semiconductor chip and exposes a lateral surface of the lower semiconductor chip.
17. The semiconductor package of claim 13 , wherein a width of the lower semiconductor chip is greater than a width of each of the plurality of semiconductor chips in a second direction parallel to the top surface of the lower semiconductor chip.
18. The semiconductor package of claim 17 , further comprising a plurality of additional bumps between the lower semiconductor chip and a lowermost semiconductor chip among the plurality of semiconductor chips,
wherein the lower semiconductor chip comprises a plurality of lower through electrodes, and
wherein the lower semiconductor chip is connected to the plurality of semiconductor chips through the plurality of lower through electrodes and the plurality of additional bumps.
19. The semiconductor package of claim 13 , further comprising:
a first substrate; and
an additional semiconductor chip on the first substrate,
wherein the lower semiconductor chip is on the first substrate and horizontally spaced apart from the additional semiconductor chip, and
wherein the second mold layer is vertically spaced apart from the first substrate.